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公开(公告)号：US20070063735A1
公开(公告)日：2007-03-22
申请号：US11526612
申请日：2006-09-26
IPC分类号： H03K19/0175
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.
摘要翻译： 一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及 缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入 所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。
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公开(公告)号：US07112999B2
公开(公告)日：2006-09-26
申请号：US11124060
申请日：2005-05-09
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.
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公开(公告)号：US20060120441A1
公开(公告)日：2006-06-08
申请号：US11288349
申请日：2005-11-29
CPC分类号： H04B1/71637
摘要： With the objective of enhancing receiving performance of a receiver with respect to pulse signals spread by spread codes, the receiver comprises an RF front-end section which performs amplification, an AD converter section which AD-converts signals outputted from the RF front-end section, a baseband section which inversely spreads the output of the AD converter section and performs signal detection and demodulation thereon, a reception environment measuring section which measures reception environment using the input signals of the baseband section, and a parameter setting section which sets parameters for respective parts on the basis of signals outputted from the reception environment measuring section. The parameter setting section sets the parameters for the respective parts to the optimum according to the environmental condition measured by the reception environment measuring section.
摘要翻译： 为了提高接收机相对于由扩展码扩展的脉冲信号的接收性能，接收机包括执行放大的RF前端部分，对从RF前端部分输出的信号进行AD转换的AD转换器部分 基带部分，其对AD转换器部分的输出进行反扩频并对其进行信号检测和解调;接收环境测量部分，其使用基带部分的输入信号测量接收环境;以及参数设置部分，其设置各自的参数 基于从接收环境测量部输出的信号。 参数设定部根据由接收环境测定部测定的环境条件，将各部分的参数设定为最佳。
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公开(公告)号：US20050007183A1
公开(公告)日：2005-01-13
申请号：US10911664
申请日：2004-08-05
IPC分类号： H03K3/01 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00323 , H03K19/00384 , H03K19/018585
摘要： A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.
摘要翻译： 半导体集成电路器件包括执行预定处理的逻辑电路，向逻辑电路提供时钟信号的时钟发生器以及控制逻辑电路的操作速度的速度控制器。 在逻辑电路工作时，时钟发生器通过频率控制信号来改变时钟信号的频率，速度控制器根据时钟信号的变化来控制逻辑电路的工作速度。
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95.发明授权Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit 有权包括衬底偏置控制器和限流电路的半导体集成电路器件公开(公告)号：US06778002B2
公开(公告)日：2004-08-17
申请号：US10207903
申请日：2002-07-31
IPC分类号： H03K301
CPC分类号： G05F3/205
摘要： In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.
摘要翻译： 在半导体集成电路装置中，为了实现高速化以及优异的产品成品率和可用性，在减小电路规模并提高产品产率和可靠性的同时，将由CMOS元件构成的主电路耦合到速度 用于形成对应于其工作速度的速度信号的监视器电路和用于响应速度监视电路向主电路提供相应衬底偏置电压的衬底偏置控制器。 还结合衬底偏置控制器提供限流电路，以防止由于偏置电压引起的电流溢出。
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公开(公告)号：US06774705B2
公开(公告)日：2004-08-10
申请号：US09811387
申请日：2001-03-20
IPC分类号： H03K301
CPC分类号： H03K19/00384
摘要： A semiconductor integrated circuit device includes control circuits FRQCNT, VDDCNT and VBBCNT that generate the optimum clock signal, supply voltage and substrate bias respectively and then supply them to a main circuit LSI. This operation makes it possible to suppress the variations of a CMOS circuit characteristic, thereby improving the circuit performance. Further, the low power consumption is realized without degrading the operating speed of the CMOS circuit or increasing the power consumption of the CMOS circuit.
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公开(公告)号：US06300807B1
公开(公告)日：2001-10-09
申请号：US09388438
申请日：1999-09-02
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Takeshi Sakata , Satoru Hanzawa , Hiroyuki Mizuno , Kiyoshi Hasegawa , Masaru Kokubo , Hirokazu Aoki
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Takeshi Sakata , Satoru Hanzawa , Hiroyuki Mizuno , Kiyoshi Hasegawa , Masaru Kokubo , Hirokazu Aoki
IPC分类号： H03L706
CPC分类号： H04L7/0008 , G06F1/10 , H03K5/135 , H04L7/0037
摘要： A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.
摘要翻译： 使用同步镜延迟电路的定时控制电路装置即使在负载变化时也保持时钟信号同步。 参考时钟信号（clkin 11）被输入到定时控制电路（SMDF 14），用于产生内部时钟（dclk12），然后通过缓冲器（BUF 15）产生外部时钟（clkout 13）。 外部时钟信号被反馈到定时控制电路（SMDF14），用于产生内部时钟信号，以使外部时钟信号与参考时钟信号同相。 定时控制电路设置有用于检测内部时钟信号和外部时钟信号之间的相位差的电路（FDA 21，MCC 22）以及用于控制延迟时间的延迟电路（DCL 24），因此 延迟电路（DCL24）可以根据检测到的相位差来改变延迟时间。
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98.发明授权
公开(公告)号：US4659208A
公开(公告)日：1987-04-21
申请号：US757784
申请日：1985-07-22
CPC分类号： G03G15/302 , G03B27/6257
摘要： A copying apparatus which performs either of two scanning functions depending on the size of original documents. In case of a large-size document, a scanning operation therefor is carried out by moving the document relative to the stationary fixed optical system responsive to selection of such scanning operation. The selection is effective only when the large-size document is detected.
摘要翻译： 根据原始文件的尺寸执行两种扫描功能的复印装置。 在大尺寸文件的情况下，通过根据这种扫描操作的选择来移动文件相对于固定固定光学系统来执行扫描操作。 只有当检测到大尺寸文档时，才能进行选择。
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公开(公告)号：US3949183A
公开(公告)日：1976-04-06
申请号：US488777
申请日：1974-07-15
申请人： Kazuo Usami , Masayuki Miyazaki , Akemi Hizikata
发明人： Kazuo Usami , Masayuki Miyazaki , Akemi Hizikata
CPC分类号： H05B6/1209
摘要： An induction heating apparatus for induction-heating a heated element such as a cooking pot by an exciter which forms an alternating magnetic field excited by the standard line frequency. The apparatus comprises a cover plate made of a high resistant non-magnetic metal, preferably stainless steel, placed above said exciter to face said heated element. Preferred embodiments of the cover plate for absorbing thermal expansion include the formation of a rim between a central region (supporting surface) on which is placed said heated element and a peripheral region; formation of a circular projection or a groove projecting upwardly or downwardly at a peripheral part in said central region or formation of a curved surface in the inner region of the peripheral circular projection or groove of said central region.
摘要翻译： 感应加热装置，其通过由形成由标准线路频率激发的交变磁场的激励器对加热元件如烹饪锅进行感应加热。 该装置包括由位于所述激励器上方以面对所述加热元件的高阻非磁性金属（优选不锈钢）制成的盖板。 用于吸收热膨胀的盖板的优选实施例包括在放置所述加热元件的中心区域（支撑表面）和周边区域之间形成边缘; 在所述中心区域的周边部分处形成圆形突起或者向上或向下突出的凹槽或在所述中心区域的周边圆形突起或凹槽的内部区域中形成弯曲表面。
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