-
公开(公告)号：US20080116934A1
公开(公告)日：2008-05-22
申请号：US11970370
申请日：2008-01-07
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.
摘要翻译： 一种半导体器件，包括具有多个反相器的频率可变振荡电路，每个反相器具有PMOS晶体管和NMOS晶体管，第一衬底偏置发生器包括第一相位/频率比较电路，其比较来自频率变量 具有参考时钟信号的振荡电路，并响应于此产生第一衬底偏置电压，第一衬底偏置电压被提供给振荡电路中的PMOS晶体管的衬底，第二衬底偏置发生器包括第二相/频率比较电路 其将来自频率可变振荡电路的输出信号与参考时钟进行比较，并响应于此产生第二衬底偏置电压，第二衬底偏置电压被提供给振荡电路中的NMOS晶体管的衬底。
-
公开(公告)号：US20070063735A1
公开(公告)日：2007-03-22
申请号：US11526612
申请日：2006-09-26
IPC分类号： H03K19/0175
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.
摘要翻译： 一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及 缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入 所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。
-
公开(公告)号：US07112999B2
公开(公告)日：2006-09-26
申请号：US11124060
申请日：2005-05-09
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.
-
公开(公告)号：US20050007183A1
公开(公告)日：2005-01-13
申请号：US10911664
申请日：2004-08-05
IPC分类号： H03K3/01 , H03K19/003 , H03K19/0185
CPC分类号： H03K19/00323 , H03K19/00384 , H03K19/018585
摘要： A semiconductor integrated circuit device includes a logic circuit to perform a predetermined process, a clock generator to supply a clock signal to the logic circuit, and a speed controller to control the operation speed of the logic circuit. The clock generator changes the frequency of the clock signal by a frequency control signal during a time when the logic circuit is operating, and the speed controller controls the operating speed of the logic circuit in accordance with a change in the clock signal.
摘要翻译： 半导体集成电路器件包括执行预定处理的逻辑电路，向逻辑电路提供时钟信号的时钟发生器以及控制逻辑电路的操作速度的速度控制器。 在逻辑电路工作时，时钟发生器通过频率控制信号来改变时钟信号的频率，速度控制器根据时钟信号的变化来控制逻辑电路的工作速度。
-
5.发明授权Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit 有权包括衬底偏置控制器和限流电路的半导体集成电路器件公开(公告)号：US06778002B2
公开(公告)日：2004-08-17
申请号：US10207903
申请日：2002-07-31
IPC分类号： H03K301
CPC分类号： G05F3/205
摘要： In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit. A current limiting circuit is also provided in conjunction with the substrate bias controller to prevent an overflow of current due to bias voltage.
摘要翻译： 在半导体集成电路装置中，为了实现高速化以及优异的产品成品率和可用性，在减小电路规模并提高产品产率和可靠性的同时，将由CMOS元件构成的主电路耦合到速度 用于形成对应于其工作速度的速度信号的监视器电路和用于响应速度监视电路向主电路提供相应衬底偏置电压的衬底偏置控制器。 还结合衬底偏置控制器提供限流电路，以防止由于偏置电压引起的电流溢出。
-
公开(公告)号：US06774705B2
公开(公告)日：2004-08-10
申请号：US09811387
申请日：2001-03-20
IPC分类号： H03K301
CPC分类号： H03K19/00384
摘要： A semiconductor integrated circuit device includes control circuits FRQCNT, VDDCNT and VBBCNT that generate the optimum clock signal, supply voltage and substrate bias respectively and then supply them to a main circuit LSI. This operation makes it possible to suppress the variations of a CMOS circuit characteristic, thereby improving the circuit performance. Further, the low power consumption is realized without degrading the operating speed of the CMOS circuit or increasing the power consumption of the CMOS circuit.
-
公开(公告)号：US06300807B1
公开(公告)日：2001-10-09
申请号：US09388438
申请日：1999-09-02
申请人： Masayuki Miyazaki , Koichiro Ishibashi , Takeshi Sakata , Satoru Hanzawa , Hiroyuki Mizuno , Kiyoshi Hasegawa , Masaru Kokubo , Hirokazu Aoki
发明人： Masayuki Miyazaki , Koichiro Ishibashi , Takeshi Sakata , Satoru Hanzawa , Hiroyuki Mizuno , Kiyoshi Hasegawa , Masaru Kokubo , Hirokazu Aoki
IPC分类号： H03L706
CPC分类号： H04L7/0008 , G06F1/10 , H03K5/135 , H04L7/0037
摘要： A timing-control circuit device, which uses a synchronous mirror delay circuit, for keeping the synchronization between clock signals in phase even at a load change. A reference clock signal (clkin 11) is entered to a timing-control circuit (SMDF 14) and used to generate an internal clock (dclk 12), then generates an external clock (clkout 13) through a buffer (BUF 15). The external clock signal is fed back to the timing-control circuit (SMDF 14) and used to generate an internal clock signal so as to synchronize the external clock signal in phase with the reference clock signal. The timing-control circuit is provided with a circuit (FDA 21, MCC 22) for detecting a phase difference between the internal clock signal and the external clock signal, as well as a delay circuit (DCL 24) for controlling a delay time, so that the delay circuit (DCL 24) can change the delay time according to the detected phase difference.
摘要翻译： 使用同步镜延迟电路的定时控制电路装置即使在负载变化时也保持时钟信号同步。 参考时钟信号（clkin 11）被输入到定时控制电路（SMDF 14），用于产生内部时钟（dclk12），然后通过缓冲器（BUF 15）产生外部时钟（clkout 13）。 外部时钟信号被反馈到定时控制电路（SMDF14），用于产生内部时钟信号，以使外部时钟信号与参考时钟信号同相。 定时控制电路设置有用于检测内部时钟信号和外部时钟信号之间的相位差的电路（FDA 21，MCC 22）以及用于控制延迟时间的延迟电路（DCL 24），因此 延迟电路（DCL24）可以根据检测到的相位差来改变延迟时间。
-
公开(公告)号：US07397282B2
公开(公告)日：2008-07-08
申请号：US11526612
申请日：2006-09-26
IPC分类号： H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.
摘要翻译： 一种半导体集成电路器件，包括在半导体衬底上包含MIS晶体管的逻辑电路，用于控制逻辑电路中的MIS晶体管的阈值电压的控制电路，在半导体衬底上包含MIS晶体管的振荡电路，以及 缓冲电路，控制电路比较振荡输出的频率和时钟信号的频率，输出第一控制信号，第一控制信号控制振荡电路的MIS晶体管的阈值电压，缓冲电路输入 所述第一控制信号输出对应于所述第一控制信号的第二控制信号，所述第二控制信号控制所述逻辑电路的所述MIS晶体管的阈值电压。
-
公开(公告)号：US06906551B2
公开(公告)日：2005-06-14
申请号：US10154956
申请日：2002-05-28
IPC分类号： H01L27/092 , H01L27/105 , H03K3/01
CPC分类号： H01L27/0207 , H01L27/092 , H01L27/105 , H03K3/011 , H03K3/0315 , H03K19/0016
摘要： A semiconductor integrated circuit device comprising a logical circuit including a MIS transistor formed on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor forming the logical circuit, an oscillation circuit including a MIS transistor formed on the semiconductor substrate, the oscillation circuit being constructed so that the frequency of an oscillation output thereof can be made variable, and a buffer circuit, in which the control circuit is supplied with a clock signal having a predetermined frequency and the oscillation output of the oscillation circuit so that the control circuit compares the frequency of the oscillation output and the frequency of the clock signal to output a first control signal, the oscillation circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal, the control of the frequency of the oscillation output being performed in such a manner that the first control signal controls a threshold voltage of the MIS transistor forming the oscillation circuit, and the buffer circuit is constructed so that it is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor forming the logical circuit.
摘要翻译： 一种半导体集成电路器件，包括一个逻辑电路，该逻辑电路包括形成在半导体衬底上的MIS晶体管，用于控制形成逻辑电路的MIS晶体管的阈值电压的控制电路，包括形成在半导体衬底上的MIS晶体管的振荡电路， 振荡电路被构造成使得其振荡输出的频率可以变化;以及缓冲电路，其中向控制电路提供具有预定频率的时钟信号和振荡电路的振荡输出，使得控制 电路将振荡输出的频率和时钟信号的频率进行比较以输出第一控制信号，振荡电路由第一控制信号控制，使得振荡输出的频率对应于时钟信号的频率， 控制振荡输出的频率 d，使得第一控制信号控制形成振荡电路的MIS晶体管的阈值电压，并且缓冲电路被构造成输入第一控制信号以输出与第一控制相对应的第二控制信号 信号，所述第二控制信号控制构成所述逻辑电路的所述MIS晶体管的阈值电压。
-
公开(公告)号：US06833750B2
公开(公告)日：2004-12-21
申请号：US10321616
申请日：2002-12-18
IPC分类号： G05F110
摘要： A semiconductor integrated circuit and power control method use one of a supply voltage of the circuit and a delay time of the circuit to control a substrate bias voltage applied to a substrate of an insulated gate field effect transistor. High speed operation, consuming a small amount of power, is achieved. A CMOS circuit has a widened operating voltage range, with reduced leak currents in a standby mode in a range of high supply voltage, reducing power consumption of the CMOS circuit, and increasing operating speed of the CMOS circuit in the range of low supply voltage.
摘要翻译： 半导体集成电路和功率控制方法使用电路的电源电压和电路的延迟时间之一来控制施加到绝缘栅场效应晶体管的衬底的衬底偏置电压。 实现高速运转，消耗少量电力。 CMOS电路具有加宽的工作电压范围，在待机模式下在高电源电压范围内减小泄漏电流，降低CMOS电路的功耗，以及在低电源电压范围内提高CMOS电路的工作速度。
-
-
-
-
-
-
-
-
-
搜索结果
220 条记录 (耗时 0.028 秒)