公开(公告)号：US12211143B2

公开(公告)日：2025-01-28

申请号：US18447155

申请日：2023-08-09

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

IPC: G06T15/80 ,  G06T15/00 ,  G06T15/50 ,  G06T17/20

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

公开(公告)号：US20240078735A1

公开(公告)日：2024-03-07

申请号：US18067837

申请日：2022-12-19

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Xuefeng Tang ,  Vishwanath Shashikant Nikam ,  Nigel Poole ,  Kalyan Kumar Bhiravabhatla ,  Fei Xu ,  Zilin Ying

IPC: G06T15/00

CPC classification number: G06T15/005

Abstract: A sliced graphics processing unit (GPU) architecture in processor-based devices is disclosed. In some aspects, a GPU based on a sliced GPU architecture includes multiple hardware slices. The GPU further includes a command processor (CP) circuit and an unslice primitive controller (PC_US). Upon receiving a graphics instruction from a central processing unit (CPU), the CP circuit determines a graphics workload, and transmits the graphics workload to the PC_US. The PC_US then partitions the graphics workload into multiple subbatches and distributes each subbatch to a PC_S of a hardware slice for processing.

公开(公告)号：US11893654B2

公开(公告)日：2024-02-06

申请号：US17373704

申请日：2021-07-12

Applicant: QUALCOMM Incorporated

Inventor： Sreyas Kurumanghat ,  Kalyan Kumar Bhiravabhatla ,  Andrew Evan Gruber ,  Tao Wang ,  Baoguang Yang ,  Pavan Kumar Akkaraju

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/40

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/405

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a portion of a GPU to include at least one depth processing block, the at least one depth processing block being associated with at least one depth buffer. The apparatus may also identify one or more depth passes of each of a plurality of graphics workloads, the plurality of graphics workloads being associated with a plurality of frames. Further, the apparatus may process each of the one or more depth passes in the portion of the GPU including the at least one depth processing block, each of the one or more depth passes being processed by the at least one depth processing block, the one or more depth passes being associated with the at least one depth buffer.

公开(公告)号：US11769294B2

公开(公告)日：2023-09-26

申请号：US17522178

申请日：2021-11-09

Applicant: QUALCOMM Incorporated

Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

IPC: G06T15/80 ,  G06T17/20 ,  G06T15/00 ,  G06T15/50

CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005 ,  G06T15/50 ,  G06T17/20

Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

公开(公告)号：US11763419B2

公开(公告)日：2023-09-19

申请号：US18046901

申请日：2022-10-14

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Yun Du

IPC: G06T15/50 ,  G06T1/60 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/30098 ,  G06T1/20

Abstract: This disclosure provides systems, devices, apparatus and methods, including computer programs encoded on storage media, for GPR optimization in a GPU based on a GPR release mechanism. More specifically, a GPU may determine at least one unutilized branch within an executable shader based on constants defined for the executable shader. Based on the at least one unutilized branch, the GPU may further determine a number of GPRs that can be deallocated from previously allocated GPRs. The GPU may deallocate, for a subsequent thread within a draw call, the number of GPRs from the previously allocated GPRs during execution of the executable shader based on the determined number of GPRs to be deallocated.

公开(公告)号：US11657471B2

公开(公告)日：2023-05-23

申请号：US17356434

申请日：2021-06-23

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chihong Zhang ,  Jian Jiang ,  Gang Zhong ,  Baoguang Yang ,  Yang Xia ,  Chun Yu ,  Eric Demers

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may generate a table including a plurality of entries to store data associated with at least one of a constant value or an immediate value. The apparatus may also process, upon generating the table, first data including at least one of a constant value or an immediate value. Further, the apparatus may store, in the generated table, at least one of the constant value or the immediate value of the first data. The apparatus may also transmit, upon storing at least one of the constant value or the immediate value in the table, the table including the stored at least one of the constant value or the immediate value of the first data.

公开(公告)号：US11645145B2

公开(公告)日：2023-05-09

申请号：US16716247

申请日：2019-12-16

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber

IPC: G06F11/07 ,  G06T1/60 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0871 ,  G06F12/0882 ,  G09G5/00

CPC classification number: G06F11/0793 ,  G06F9/30047 ,  G06F9/3861 ,  G06F9/5016 ,  G06F9/5022 ,  G06F9/544 ,  G06F11/0772 ,  G06F12/0871 ,  G06F12/0882 ,  G06T1/60 ,  G09G5/001

Abstract: The present disclosure relates to methods and apparatus for display processing. For example, disclosed techniques facilitate speculative page fault handling in a GPU. Aspects of the present disclosure can perform a graphics operation associated with using a set of constants within a flow control. Aspects of the present disclosure can also query a first memory to determine whether memory addresses associated with the set of constants are allocated at a constant buffer of the first memory. Further, aspects of the present disclosure can set a page fault indicator to a true value when the query indicates that at least one memory address associated with the set of constants is unallocated at the constant buffer, and set the page fault indicator to a false value otherwise.

公开(公告)号：US11631215B2

公开(公告)日：2023-04-18

申请号：US16816150

申请日：2020-03-11

Applicant: QUALCOMM Incorporated

Inventor： Andrew Evan Gruber ,  Krishnaiah Gummidipudi ,  Pavan Kumar Akkaraju ,  Kalyan Kumar Bhiravabhatla ,  Ankit Kumar Singh ,  Sharad Raj

IPC: G06T15/50 ,  G06T1/20 ,  G06T15/00 ,  G06T7/00 ,  G06T17/10 ,  G06T17/20

Abstract: The present disclosure relates to methods and apparatus for graphics processing. The present disclosure can calculate a center-edge distance of a first pixel, the center-edge distance of the first pixel equal to a distance from a first pixel center to one or more edges of a first primitive. Additionally, the present disclosure can store the center-edge distance of the first pixel when the first primitive is visible in a scene. The present disclosure can also determine an amount of overlap between the first pixel and the first primitive. Further, the present disclosure can blend a color of the first pixel with a color of a second pixel based on at least one of the center-edge distance of the first pixel or the amount of overlap between the first pixel and the first primitive.

公开(公告)号：US11615504B2

公开(公告)日：2023-03-28

申请号：US17229697

申请日：2021-04-13

Applicant: QUALCOMM Incorporated

Inventor： Vishwanath Shashikant Nikam ,  Kalyan Kumar Bhiravabhatla ,  Suvam Chatterjee ,  Siva Satyanarayana Kola ,  Abhishek Lal ,  Andrew Evan Gruber

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

公开(公告)号：US11055808B2

公开(公告)日：2021-07-06

申请号：US16455641

申请日：2019-06-27

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chun Yu ,  Zilin Ying

IPC: G06T1/20 ,  G06T1/60

Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, the apparatus can determine one or more context states of at least one context register in each of multiple wave slots. The apparatus can also send information corresponding to the one or more context states in one of the multiple wave slots to a context queue. Further, the apparatus can convert the information corresponding to the one or more context states to context information compatible with the context queue. The apparatus can also store the context information compatible with the context queue in the context queue. In some aspects, the apparatus can send the context information compatible with the context queue to one of the multiple wave slots. Additionally, the apparatus can convert the context information compatible with the context queue to the information corresponding to the one or more context states.