公开(公告)号：US11094032B2

公开(公告)日：2021-08-17

申请号：US16734252

申请日：2020-01-03

Applicant: QUALCOMM INCORPORATED

Inventor： Yun Du ,  Chun Yu ,  Andrew Evan Gruber ,  Zilin Ying ,  Baoguang Yang

IPC: G06T1/20 ,  G06T11/00

Abstract: Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit.

公开(公告)号：US20200273142A1

公开(公告)日：2020-08-27

申请号：US16282003

申请日：2019-02-21

Applicant: QUALCOMM Incorporated

Inventor： Shambhoo Khandelwal ,  Tao Wang ,  Shangmei Yu ,  Jing Gao ,  Jian Liang ,  Andrew Evan Gruber ,  Chun Yu

IPC: G06T1/60 ,  G06F3/06

Abstract: The described techniques provide for bin-based rendering where the scene geometry in a frame is subdivided into bins or tiles, and bins are resolved concurrently with the rendering of a next bin. For example, a graphics processing unit (GPU) may process an entire image and sort transactions (e.g., rasterized primitives, such as triangles) into bins. For the rendering of each transaction, a device may identify a memory address of a memory block (e.g., a unit or portion of internal GPU memory (GMEM)) the transaction will be written (i.e., rendered) to. The device may thus prepare the memory block for rendering (e.g., by performing a resolve operation, a clear operation, or an unresolve operation on the memory block), such that the memory block is prepared prior to rendering of the particular transaction. As such, transactions of a bin may be resolved concurrently with rendering of transactions of a next bin.

公开(公告)号：US12229215B2

公开(公告)日：2025-02-18

申请号：US18487918

申请日：2023-10-16

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Gang Zhong ,  Fei Wei ,  Yibin Zhang ,  Jing Han ,  Hongjiang Shang ,  Elina Kamenetskaya ,  Minjie Huang ,  Alexei Vladimirovich Bourd ,  Chun Yu ,  Andrew Evan Gruber ,  Eric Demers

IPC: G06F17/16 ,  G06F7/57 ,  G06F9/30 ,  G06F9/38

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

公开(公告)号：US11657471B2

公开(公告)日：2023-05-23

申请号：US17356434

申请日：2021-06-23

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chihong Zhang ,  Jian Jiang ,  Gang Zhong ,  Baoguang Yang ,  Yang Xia ,  Chun Yu ,  Eric Demers

IPC: G06T1/20 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may generate a table including a plurality of entries to store data associated with at least one of a constant value or an immediate value. The apparatus may also process, upon generating the table, first data including at least one of a constant value or an immediate value. Further, the apparatus may store, in the generated table, at least one of the constant value or the immediate value of the first data. The apparatus may also transmit, upon storing at least one of the constant value or the immediate value in the table, the table including the stored at least one of the constant value or the immediate value of the first data.

公开(公告)号：US11055808B2

公开(公告)日：2021-07-06

申请号：US16455641

申请日：2019-06-27

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Andrew Evan Gruber ,  Chun Yu ,  Zilin Ying

IPC: G06T1/20 ,  G06T1/60

Abstract: The present disclosure relates to methods and apparatus for graphics processing. In some aspects, the apparatus can determine one or more context states of at least one context register in each of multiple wave slots. The apparatus can also send information corresponding to the one or more context states in one of the multiple wave slots to a context queue. Further, the apparatus can convert the information corresponding to the one or more context states to context information compatible with the context queue. The apparatus can also store the context information compatible with the context queue in the context queue. In some aspects, the apparatus can send the context information compatible with the context queue to one of the multiple wave slots. Additionally, the apparatus can convert the context information compatible with the context queue to the information corresponding to the one or more context states.

公开(公告)号：US20180189179A1

公开(公告)日：2018-07-05

申请号：US15423889

申请日：2017-02-03

Applicant: QUALCOMM Incorporated

Inventor： Yun Li ,  Jian Liang ,  Fei Xu ,  Zhen Chen ,  Chun Yu ,  Tao Wang

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0846

CPC classification number: G06F12/0811 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/455

Abstract: A cache memory may receive, from a client, a request for a long cache line of data. The cache memory may receive, from a memory, the requested long cache line of data. The cache memory may store the requested long cache line of data into a plurality of data stores across a plurality of memory banks as a plurality of short cache lines of data distributed across the plurality of data stores in the cache memory. The cache memory may also store a plurality of tags associated with the plurality of short cache lines of data into one of a plurality of tag stores in the plurality of memory banks.

公开(公告)号：US20180165092A1

公开(公告)日：2018-06-14

申请号：US15379195

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Liang Han ,  Lin Chen ,  Chihong Zhang ,  Hongjiang Shang ,  Jing Wu ,  Zilin Ying ,  Chun Yu ,  Guofang Jiao ,  Andrew Gruber ,  Eric Demers

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems and techniques are disclosed for general purpose register dynamic allocation based on latency associated with of instructions in processor threads. A streaming processor can include a general purpose registers configured to stored data associated with threads, and a thread scheduler configured to receive allocation information for the general purpose registers, the information describing general purpose registers that are to be assigned as persistent general purpose registers (pGPRs) and volatile general purpose registers (vGPRs). The plurality of general purpose registers can be allocated according to the received information. The streaming processor can include the general purpose registers allocated according to the received information, the allocated based on execution latencies of instructions included in the threads.

公开(公告)号：US12229864B2

公开(公告)日：2025-02-18

申请号：US17817815

申请日：2022-08-05

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Eric Demers ,  Andrew Evan Gruber ,  Chun Yu ,  Baoguang Yang ,  Chihong Zhang ,  Yuehai Du ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar ,  Gang Zhong ,  Zilin Ying ,  Fei Wei

IPC: G06T15/00 ,  G06T15/80

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.

公开(公告)号：US12067666B2

公开(公告)日：2024-08-20

申请号：US17664033

申请日：2022-05-18

Applicant: QUALCOMM Incorporated

Inventor： Yun Du ,  Eric Demers ,  Andrew Evan Gruber ,  Chun Yu ,  Chihong Zhang ,  Baoguang Yang ,  Yuehai Du ,  Gang Zhong ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar

IPC: G06T15/00 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/60

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.

公开(公告)号：US09799089B1

公开(公告)日：2017-10-24

申请号：US15162272

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Lin Chen ,  Yun Du ,  Andrew Evan Gruber ,  Guofang Jiao ,  Chun Yu ,  David Rigel Garcia Garcia

IPC: G06T1/20 ,  G06T15/80 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/80

Abstract: A method for processing data in a graphics processing unit including receiving a code block of instructions common to a plurality of groups of threads of a shader, executing the code block of instructions common to the plurality of groups of threads of the shader creating a result by a first group of threads of the plurality of groups of threads, storing the result of the code block of instructions common to the plurality of groups of threads of the shader in on-chip random access memory (RAM), the on-chip RAM accessible by each of the plurality of groups of threads, and upon a determination that storing the result of the code block of instructions common to the plurality of groups of threads of the shader has completed, returning the result of the code block of instructions common to the plurality of groups of threads of the shader from on-chip RAM.