公开(公告)号：US08217678B1

公开(公告)日：2012-07-10

申请号：US12834404

申请日：2010-07-12

申请人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

发明人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy L. Lee

IPC分类号： H03K19/173

CPC分类号： H03K19/177

摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

摘要翻译： 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

公开(公告)号：US08200471B2

公开(公告)日：2012-06-12

申请号：US12534103

申请日：2009-07-31

申请人： David Lewis ,  Thomas Yau-Tsun Wong

发明人： David Lewis ,  Thomas Yau-Tsun Wong

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： Apparatus and methods for calculating power consumption of circuitry within integrated circuits (ICs), such as programmable logic devices (PLDs) are disclosed and described. A method of estimating power consumption of a circuit in an IC includes decomposing the IC into a plurality of overlapping blocks. Each block in the plurality of blocks includes a portion of the circuitry in the IC. The method further includes estimating power consumption of each block in the plurality of blocks, and estimating power consumption of the IC based on the power consumption of the plurality of blocks.

摘要翻译： 公开并描述了用于计算诸如可编程逻辑器件（PLD）的集成电路（IC）内的电路的功耗的装置和方法。 估计IC中的电路的功耗的方法包括将IC分解为多个重叠块。 多个块中的每个块包括IC中的电路的一部分。 该方法还包括估计多个块中的每个块的功率消耗，以及基于多个块的功耗来估计IC的功耗。

公开(公告)号：US08115530B2

公开(公告)日：2012-02-14

申请号：US12976752

申请日：2010-12-22

申请人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

IPC分类号： H03K3/00

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器显示出通过条件降低的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。

公开(公告)号：US20110227625A1

公开(公告)日：2011-09-22

申请号：US13149774

申请日：2011-05-31

申请人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

发明人： David Lewis ,  Jeffrey Christopher Chromczak ,  Ryan Fung

IPC分类号： H03K3/02

CPC分类号： H03K3/356008 ,  H03K3/0375 ,  H03K19/00315 ,  H03K19/17764

摘要： An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

摘要翻译： 集成电路（IC）包括一组亚稳态硬化存储电路。 每个亚硬化存储电路可以包括：（a）脉冲宽度失真电路; （b）由标称电源电压供电的第一电路和由高于标称电源电压供电的第二电路; （c）逆变器和偏置电路，其中所述偏置电路基于所述逆变器的中间状态提供偏置电流以解决所述逆变器的亚稳态; 或（d）锁存器和动态偏置电路，其使电流注入到锁存器中以解决闩锁的亚稳态。

公开(公告)号：USD634733S1

公开(公告)日：2011-03-22

申请号：US29356041

申请日：2010-02-18

申请人： David Lewis

设计人： David Lewis

公开(公告)号：US07911230B1

公开(公告)日：2011-03-22

申请号：US12425342

申请日：2009-04-16

申请人： James Schleicher ,  Richard Yuan ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Gregg Baeckler ,  David Lewis ,  Mike Hutton ,  Andy Lee ,  Rahul Saini ,  Henry Kim

发明人： James Schleicher ,  Richard Yuan ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Gregg Baeckler ,  David Lewis ,  Mike Hutton ,  Andy Lee ,  Rahul Saini ,  Henry Kim

IPC分类号： H03K19/173

CPC分类号： H03K19/17728 ,  G06F7/50 ,  H03K19/017581

摘要： Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

摘要翻译： 公开了可以提供多个有利特征的逻辑元件（LE）。 例如，LE可以被配置为实现寄存器打包和/或可破碎的查找表。

公开(公告)号：US07872512B2

公开(公告)日：2011-01-18

申请号：US12060795

申请日：2008-04-01

申请人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  David Cashman ,  Jeffrey Christopher Chromczak

IPC分类号： H03K3/289

CPC分类号： H03K3/0375

摘要： Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths.

摘要翻译： 可配置的借位触发器可以基于可配置的脉冲生成电路和脉冲锁存器。 电路可以使用控制产生的时钟脉冲的宽度的自定时架构，使得由时钟脉冲控制的脉冲锁存器具有降低的竞争条件的风险。 可以提供锁存电路，其基于与脉冲锁存器串联连接的脉冲锁存器和附加锁存器。 在集成电路中存在竞争条件的可能性的情况下，附加锁存器可以被切换成使用，以将锁存电路转换成边沿触发的触发器。 时钟树可以提供可配置的短路结构，有助于减少时钟偏移。 低竞争时钟驱动器可能会将信号驱动到时钟树路径上。

公开(公告)号：US20100284408A1

公开(公告)日：2010-11-11

申请号：US12778413

申请日：2010-05-12

申请人： David Lewis ,  Howard Gurney

发明人： David Lewis ,  Howard Gurney

IPC分类号： H04L12/56

CPC分类号： H04N21/4383 ,  H04N21/42646 ,  H04N21/42661 ,  H04N21/42669 ,  H04N21/42692 ,  H04N21/434 ,  H04N21/44004

摘要： A system comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder. The second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.

摘要翻译： 一种系统，包括用于从外部源接收传输流的第一输入装置，用于从存储器接收输入的第二输入装置，用于将第一和第二输入装置连接到被配置为向解码器提供输出流的接口的装置 。 第二输入装置被布置成以这样的形式向接口提供输出，使得接口不区分来自第一和第二输入装置的输出。

公开(公告)号：US07746100B2

公开(公告)日：2010-06-29

申请号：US12111142

申请日：2008-04-28

申请人： David Lewis ,  Jeffrey Christopher Chromczak

发明人： David Lewis ,  Jeffrey Christopher Chromczak

IPC分类号： H03K19/177 ,  G06F7/42

CPC分类号： G06F7/506 ,  G06F2207/4812

摘要： Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal may be used in switching redundant circuitry into place bypassing the defect. The integrated circuit may contain an array of logic regions. Each logic region may contain adders and multiplexer circuitry for selectively combining the multiplexers to form larger adders. The multiplexer circuitry in each logic region may be controlled by propagate signals from the adders and by static redundancy control signals.

摘要翻译： 在包括冗余电路的集成电路上提供可配置加法器电路。 集成电路可以包含产生冗余控制信号的非易失性存储器和逻辑电路。 在制造期间，可以测试集成电路。 如果在集成电路上识别出缺陷，则冗余控制信号可用于将冗余电路切换到绕过缺陷的位置。 集成电路可以包含逻辑区域的阵列。 每个逻辑区域可以包含用于选择性地组合多路复用器以形成较大加法器的加法器和多路复用器电路。 每个逻辑区域中的复用器电路可以由来自加法器的传播信号和静态冗余控制信号来控制。

公开(公告)号：USD614481S1

公开(公告)日：2010-04-27

申请号：US29336322

申请日：2009-04-30

申请人： David Lewis

设计人： David Lewis