公开(公告)号：US20200303342A1

公开(公告)日：2020-09-24

申请号：US16895459

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chung-Hao Tsai ,  Chuei-Tang Wang

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

公开(公告)号：US20200294943A1

公开(公告)日：2020-09-17

申请号：US16886709

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Tzu-Chun Tang ,  Chieh-Yen Chen ,  Che-Wei Hsu

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q13/10 ,  H01Q1/24 ,  H01L23/31

Abstract: An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

公开(公告)号：US10777502B2

公开(公告)日：2020-09-15

申请号：US16667911

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Wei-Ting Chen

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L49/02 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

公开(公告)号：US10756052B2

公开(公告)日：2020-08-25

申请号：US16524146

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L23/544

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US10734323B2

公开(公告)日：2020-08-04

申请号：US15900808

申请日：2018-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Wen Lin ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Che-Wei Hsu

IPC: H01L23/522 ,  H01L23/538 ,  H01Q1/22 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

公开(公告)号：US10672728B2

公开(公告)日：2020-06-02

申请号：US16198857

申请日：2018-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Tzu-Chun Tang ,  Chieh-Yen Chen ,  Che-Wei Hsu

IPC: H01L27/14 ,  H01L31/00 ,  H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q13/10 ,  H01Q1/24 ,  H01L23/31

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a plurality of dies, a plurality of first conductive structures, an encapsulant, a second redistribution structure, and insulating layer, a plurality of second conductive structures, an antenna confinement structure, and a slot antenna. The dies and the first conductive structures are disposed on the first redistribution structure. The first conductive structures surround the dies. The encapsulant encapsulates the dies and the first conductive structures. The second redistribution structure is disposed on the dies, the first conductive structures, and the encapsulant. The insulating layer is over the second redistribution structure. The second conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

公开(公告)号：US20200105687A1

公开(公告)日：2020-04-02

申请号：US16198857

申请日：2018-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Tzu-Chun Tang ,  Chieh-Yen Chen ,  Che-Wei Hsu

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q13/10 ,  H01Q1/24

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a plurality of dies, a plurality of first conductive structures, an encapsulant, a second redistribution structure, and insulating layer, a plurality of second conductive structures, an antenna confinement structure, and a slot antenna. The dies and the first conductive structures are disposed on the first redistribution structure. The first conductive structures surround the dies. The encapsulant encapsulates the dies and the first conductive structures. The second redistribution structure is disposed on the dies, the first conductive structures, and the encapsulant. The insulating layer is over the second redistribution structure. The second conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

公开(公告)号：US20200066631A1

公开(公告)日：2020-02-27

申请号：US16667911

申请日：2019-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Wei-Ting Chen

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L49/02 ,  H01L21/56 ,  H01L21/768

Abstract: A semiconductor chip including a die substrate, a plurality of first bonding structures, a plurality of conductive elements, at least one integrated device, a plurality of conductive posts and a protection layer is provided. The first bonding structures are disposed on the die substrate. The conductive elements are disposed on the die substrate adjacent to the first bonding structures. The integrated device is disposed on the die substrate over the first bonding structures, wherein the integrated device includes a plurality of second bonding structures and a plurality of conductive pillars, and the second bonding structures are hybrid bonded to the first bonding structures. The conductive posts are disposed on the conductive elements and surrounding the integrated device. The protection layer is encapsulating the integrated device and the conductive posts.

公开(公告)号：US20190371781A1

公开(公告)日：2019-12-05

申请号：US16218492

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ya Huang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L27/01 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a passive device, and a package. The die has a front side and a backside opposite to each other. The package is disposed on the backside of the die. The passive device is disposed between the backside of the die and the package.

公开(公告)号：US10366966B1

公开(公告)日：2019-07-30

申请号：US15981929

申请日：2018-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.