公开(公告)号：US20240387502A1

公开(公告)日：2024-11-21

申请号：US18786526

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Tzu-Chun Tang ,  Chuei-Tang Wang

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments provide regulated power routing through various inactive features of a device. In one embodiment, such inactive features include a through via wall which can be formed in an encapsulating material of a die stack. In another embodiment, such inactive features include a heat dissipation features formed over the die stack. In another embodiment, such inactive features include dummy via blocks attached adjacent a die cube. Yet other embodiments may combine the features of these embodiments without limitation.

公开(公告)号：US11348886B2

公开(公告)日：2022-05-31

申请号：US16886709

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Tzu-Chun Tang ,  Chieh-Yen Chen ,  Che-Wei Hsu

IPC: H01L27/14 ,  H01L31/00 ,  H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q13/10 ,  H01Q1/24 ,  H01L23/31

Abstract: An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.

公开(公告)号：US20190096829A1

公开(公告)日：2019-03-28

申请号：US16035716

申请日：2018-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chun Tang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01Q1/22 ,  H01Q21/06

Abstract: A package structure includes a sub-package, a conductive structure, and at least one first antenna. The sub-package includes at least one chip. The conductive structure is bonded onto and electrically connected to the sub-package. The at least one first antenna has a vertical polarization and is electrically connected to the at least one chip, wherein the at least one first antenna is partially located in the sub-package, and the at least one first antenna is extended within the sub-package into the conductive structure.

公开(公告)号：US20190035877A1

公开(公告)日：2019-01-31

申请号：US15710847

申请日：2017-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chuei-Tang Wang ,  Tzu-Chun Tang ,  Wei-Ting Chen ,  Chieh-Yen Chen

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/28 ,  H01L25/00

Abstract: A package structure has a chip, a molding compound encapsulating the chip and an inductor structure disposed above the chip. A vertical projection of the inductor structure at least partially overlaps with a vertical projection of the chip.

公开(公告)号：US10157834B1

公开(公告)日：2018-12-18

申请号：US15706767

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chun Tang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Che-Wei Hsu

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485 ,  H01L23/66 ,  H01Q1/22 ,  H01L23/31 ,  H01L23/00 ,  H01L21/66

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

公开(公告)号：US20230154913A1

公开(公告)日：2023-05-18

申请号：US17703700

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Hao Tsai ,  Tzu-Chun Tang ,  Chuei-Tang Wang

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/367 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L23/5389 ,  H01L23/367 ,  H01L25/18 ,  H01L21/568 ,  H01L24/08

Abstract: Embodiments provide regulated power routing through various inactive features of a device. In one embodiment, such inactive features include a through via wall which can be formed in an encapsulating material of a die stack. In another embodiment, such inactive features include a heat dissipation features formed over the die stack. In another embodiment, such inactive features include dummy via blocks attached adjacent a die cube. Yet other embodiments may combine the features of these embodiments without limitation.

公开(公告)号：US11282810B2

公开(公告)日：2022-03-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L23/544

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US10777518B1

公开(公告)日：2020-09-15

申请号：US16413614

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chen-Hua Yu ,  Tzu-Chun Tang ,  Chieh-Yen Chen ,  Che-Wei Hsu

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/29 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01P3/20 ,  H01Q21/06 ,  H01Q1/22 ,  H01Q19/06

Abstract: A package structure includes a plurality of sub-package structures, a second encapsulant, a second RDL structure and a second conductive terminal. The sub-package structure includes a die, first TIVs, a first encapsulant and an antenna element. The die has a first side and a second side. The first TIVs are laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIVs. The antenna element is on the first side of the die, and on the TIVs and the first encapsulant. The second encapsulant encapsulates sidewalls of the sub-package structures. The second RDL structure is electrically connected to the plurality of sub-package structures. The second conductive terminal is electrically connected to the sub-package structures through the second RDL structure.

公开(公告)号：US20200335477A1

公开(公告)日：2020-10-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US20200294943A1

公开(公告)日：2020-09-17

申请号：US16886709

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Tzu-Chun Tang ,  Chieh-Yen Chen ,  Che-Wei Hsu

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q13/10 ,  H01Q1/24 ,  H01L23/31

Abstract: An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer.