公开(公告)号：US11467946B1

公开(公告)日：2022-10-11

申请号：US16368351

申请日：2019-03-28

申请人： Amazon Technologies, Inc.

发明人： Samuel Jacob ,  Drazen Borkovic ,  Yu Zhou ,  Mohammad El-Shabani

IPC分类号： G06F11/36 ,  G06F8/41 ,  G06N3/10

摘要： Techniques are disclosed for setting a breakpoint for debugging a neural network. User input is received by a debugger program executable by a host processor indicating a target layer of a neural network at which to halt execution of the neural network. The neural network includes a first set of instructions to be executed by a first execution engine and a second set of instructions to be executed by a second execution engine. A first halt point is set within the first set of instructions and a second halt point is set within the second set of instructions. It is then determined that operation of the first execution engine and the second execution engine has halted. It is then determined that the first execution engine has reached the first halt point. The second execution engine is then caused to move through instructions until reaching the second halt point.

公开(公告)号：US11455524B1

公开(公告)日：2022-09-27

申请号：US16114894

申请日：2018-08-28

申请人： BLUEOWL, LLC

发明人： Kenneth J. Sanchez

IPC分类号： H03M7/00 ,  G06N3/08 ,  H03M7/30 ,  G06K9/62 ,  G06F16/904 ,  G06N3/10 ,  G06N3/04

摘要： A computer-implemented method for improving compression of predictive models includes generating an unlabeled simulated data set by expanding an initial data set, and generating a labeled data set by predicting the unlabeled, simulated data set using a complex model to output a plurality of labels. The method also includes training a relatively simple neural network using the labeled data set.

公开(公告)号：US20220300826A1

公开(公告)日：2022-09-22

申请号：US17637190

申请日：2020-03-09

申请人： Google LLC

发明人： Arun Chauhan ,  Raksit Ashok ,  Dong Hyuk Woo

IPC分类号： G06N3/10 ,  G06N3/04 ,  G06V10/82 ,  G06F8/41

摘要： A compiler of a computing device is described that identifies a sequence of neural network models frequently invoked by an application of the computing device, compiles the models in that sequence, and loads a static random access memory (SRAM) of a hardware accelerator with the compiled models only when the same compiled models—from another, but same, sequence that was previously invoked—are not already present in the SRAM. This prevents unnecessary reloading of compiled models into the SRAM, thereby increasing runtime speed and conserving computational energy.

公开(公告)号：US11423315B2

公开(公告)日：2022-08-23

申请号：US16784218

申请日：2020-02-06

申请人： NATIONAL TSING HUA UNIVERSITY

发明人： Meng-Fan Chang ,  Jing-Hong Wang ,  Ta-Wei Liu

IPC分类号： G06N3/10 ,  G06N3/08 ,  G06N3/04 ,  G06F7/544

摘要： A quantization method for a plurality of partial sums of a convolution neural network based on a computing-in-memory hardware includes a probability-based quantizing step and a margin-based quantizing step. The probability-based quantizing step includes a network training step, a quantization-level generating step, a partial-sum quantizing step, a first network retraining step and a first accuracy generating step. The margin-based quantizing step includes a quantization edge changing step, a second network retraining step and a second accuracy generating step. The quantization edge changing step includes changing a quantization edge of at least one of a plurality of quantization levels. The probability-based quantizing step is performed to generate a first accuracy value, and the margin-based quantizing step is performed to generate a second accuracy value. The second accuracy value is greater than the first accuracy value.

公开(公告)号：US11423288B2

公开(公告)日：2022-08-23

申请号：US16039142

申请日：2018-07-18

申请人： Syntiant

发明人： Pieter Vorenkamp ,  Kurt F. Busch ,  Stephen W. Bailey ,  Jeremiah H. Holleman, III

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/10 ,  G06F30/36 ,  G06F30/327 ,  G06N3/08 ,  H01L21/82

摘要： Disclosed herein is a method for automatically generating an integrated circuit. The method includes receiving a behavioral description of at least the first layer of the neural network, converting the behavioral description of the first layer of the neural network into the computational graph, converting a computational graph to a circuit netlist based on a correlation of: (i) operations described in the computational graph, and (ii) an analog cell library including a plurality of predetermined circuit blocks that describe known neural network operations, generating a circuit layout that corresponds to at least a first layer of a neural network, and performing additional actions configured to cause generation of the integrated circuit based on the circuit layout. In some situations, the behavioral description defines an architecture of machine learning logic that represents at least a portion of the neural network. Additionally, in some situations, each cell of the integrated circuit includes a metal-oxide-semiconductor field-effect transistor (“MOSFET”).

公开(公告)号：US11416749B2

公开(公告)日：2022-08-16

申请号：US16216873

申请日：2018-12-11

申请人： Amazon Technologies, Inc.

发明人： Nafea Bshara ,  Thomas A. Volpe

IPC分类号： G06N3/10 ,  G06F9/30 ,  G06F9/54 ,  G06N3/063 ,  G06F9/38

摘要： An integrated circuit includes a processing engine configured to execute instructions that are synchronized using a set of events. The integrated circuit also includes a set of event registers and an age bit register. Each event in the set of events corresponds to a respective event register in the set of event registers. The age bit register includes a set of age bits, where each age bit in the age bit register corresponds to a respective event register in the set of event registers. Each age bit in the age bit register is configured to be set by an external circuit and to be cleared in response to a value change in a corresponding event register in the set of event registers. Executing the instructions by the processing engine changes a value of an event register in the set of event registers.

公开(公告)号：US20220245404A1

公开(公告)日：2022-08-04

申请号：US17719885

申请日：2022-04-13

申请人： Magic Leap, Inc.

发明人： Adrian Kaehler ,  Gary R. Bradski ,  Vijay Badrinarayanan

IPC分类号： G06K9/62 ,  G06N3/04 ,  G06N3/10 ,  G06K9/00 ,  G06F3/01 ,  G06V20/10 ,  G06V20/20 ,  G06V40/20 ,  G06T7/70 ,  G06F3/0346 ,  G06F3/04815 ,  G06N3/08 ,  G06T19/00

摘要： Disclosed herein are examples of a wearable display system capable of determining a user interface (UI) event with respect to a virtual UI device (e.g., a button) and a pointer (e.g., a finger or a stylus) using a neural network. The wearable display system can render a representation of the UI device onto an image of the pointer captured when the virtual UI device is shown to the user and the user uses the pointer to interact with the virtual UI device. The representation of the UI device can include concentric shapes (or shapes with similar or the same centers of gravity) of high contrast. The neural network can be trained using training images with representations of virtual UI devices and pointers.

公开(公告)号：US20220188619A1

公开(公告)日：2022-06-16

申请号：US17683125

申请日：2022-02-28

申请人： SYNTIANT

发明人： Kurt F. Busch ,  Jeremiah H. Holleman, III ,  Pieter Vorenkamp ,  Stephen W. Bailey

IPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06F3/16 ,  H04R25/00 ,  G06N3/10

摘要： Disclosed is a neuromorphic-processing systems including, in some embodiments, a special-purpose host processor operable as a stand-alone host processor; a neuromorphic co-processor including an artificial neural network; and a communications interface between the host processor and the co-processor configured to transmit information therebetween. The co-processor is configured to enhance special-purpose processing of the host processor with the artificial neural network. Also disclosed is a method of a neuromorphic-processing system having the special-purpose host processor and the neuromorphic co-processor including, in some embodiments, enhancing the special-purpose processing of the host processor with the artificial neural network of the co-processor. In some embodiments, the host processor is a hearing-aid processor.

公开(公告)号：US11361170B1

公开(公告)日：2022-06-14

申请号：US16744673

申请日：2020-01-16

申请人： Lilt, Inc.

发明人： Aditya Shastry ,  Spence Green ,  Joern Wuebker ,  Geza Kovacs ,  Jessy Lin ,  John DeNero

IPC分类号： G06F40/58 ,  G06N3/08 ,  G06N3/04 ,  G06N3/10

摘要： An apparatus has a network interface circuit to receive a source sentence from a network connected client device. A processor is connected to the network interface circuit. A memory is connected to the processor. The memory stores parameters of a multilingual neural review system and instructions executed by the processor to operate the multilingual neural review system trained on a corpus of source sentences, draft target sentences and corrected target sentences. The multilingual neural review system produces a corrected target sentence from a draft target sentence representing a proposed translation of the source sentence. The draft target sentence and the corrected target sentence are supplied to the network connected client device. Approval for the corrected target sentence is received from the network connected client device. Parameters of the multilingual neural review system are updated based upon the approval for the corrected target sentence.

公开(公告)号：US11361050B2

公开(公告)日：2022-06-14

申请号：US16196423

申请日：2018-11-20

申请人： Hewlett Packard Enterprise Development LP

发明人： Soumitra Chatterjee ,  Sunil Vishwanathpur Lakshminarasimha ,  Mohan Parthasarathy

IPC分类号： G06F17/16 ,  G06N3/10 ,  G06F8/41

摘要： Example implementations relate to assigning dependent matrix-vector multiplication (MVM) operations to consecutive crossbars of a dot product engine (DPE). A method can comprise grouping a first MVM operation of a computation graph with a second MVM operation of the computation graph where the first MVM operation is dependent on a result of the second MVM operation, assigning a first crossbar of a DPE to an operand of the first MVM operation, and assigning a second crossbar of the DPE to an operand of the second MVM operation, wherein the first and second crossbars are consecutive.