公开(公告)号：US07172916B2

公开(公告)日：2007-02-06

申请号：US10701552

申请日：2003-11-06

Applicant: Kyu-dong Jung ,  Chan-Bong Jun ,  Hyung Choi ,  Seok-jin Kang ,  Seog-woo Hong ,  Seok-whan Chung ,  Moon-chul Lee ,  Eun-sung Lee

Inventor： Kyu-dong Jung ,  Chan-Bong Jun ,  Hyung Choi ,  Seok-jin Kang ,  Seog-woo Hong ,  Seok-whan Chung ,  Moon-chul Lee ,  Eun-sung Lee

IPC: H01L21/00

CPC classification number: B81C1/00285

Abstract: A method and apparatus for vacuum-mounting at least one micro electro mechanical system (MEMS) on a substrate includes a gas injecting section for injecting an inert gas into a vacuum chamber; a substrate aligning section for aligning a semiconductor substrate and a cover, the cover having a cavity formed therein and a getter attached to an interior surface of the cavity; a bonding section for bonding the semiconductor substrate and the cover together; and a controlling section for controlling the substrate aligning section to align the semiconductor and the cover, for controlling the gas injecting section to inject the inert gas into the vacuum chamber, and for controlling the bonding section to bond the semiconductor substrate and the cover together after the inert gas is injected.

Abstract translation: 用于真空安装至少一个微机电系统（MEMS）在基板上的方法和装置包括用于将惰性气体注入真空室的气体注入部分; 用于对准半导体衬底和盖的衬底对准部分，所述盖具有形成在其中的空腔和附着到腔的内表面的吸气剂; 用于将半导体衬底和盖结合在一起的接合部分; 以及控制部分，用于控制衬底对准部分以对准半导体和盖子，用于控制气体注入部分以将惰性气体注入真空室中，并且用于控制接合部分将半导体衬底和盖子结合在一起，之后 注入惰性气体。

公开(公告)号：US07169684B2

公开(公告)日：2007-01-30

申请号：US10373735

申请日：2003-02-27

Applicant: Moon-chul Lee ,  In-sang Song ,  Young-tack Hong ,  Sung-hye Jeong ,  Jeong-yoo Hong

Inventor： Moon-chul Lee ,  In-sang Song ,  Young-tack Hong ,  Sung-hye Jeong ,  Jeong-yoo Hong

IPC: H01L21/30

CPC classification number: H01L27/016 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0744 ,  H01L28/10 ,  H01L28/40 ,  H01L2924/0002 ,  H03H7/00 ,  H03H7/0115 ,  H03H2001/0078 ,  H03H2001/0085 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/1006 ,  H05K2201/10545 ,  Y10S438/977 ,  H01L2924/00

Abstract: An LC device having a substrate, a support layer having upper and lower sides formed on the substrate, inductors formed on either the upper or lower side of the support layer, and capacitors formed in the opposite side of the support layer. The support layer may be formed of a low-k dielectric material, and a connection portion may be provided to connect the inductors and capacitors in the support layer. The inductors and capacitors are disposed in a stacked structure on the upper and lower sides of the low-k dielectric support layer on the substrate, so that space efficiency may be maximized on the substrate. The low-k dielectric support layer provides support between the inductors and capacitors so that substrate loss is minimized and a Q factor of the inductors is enhanced.

Abstract translation: 具有衬底的LC器件，在衬底上形成有上下侧的支撑层，形成在支撑层的上侧或下侧的电感器以及形成在支撑层的相对侧的电容器。 支撑层可以由低k介电材料形成，并且可以提供连接部分来连接支撑层中的电感器和电容器。 电感器和电容器以堆叠的结构设置在衬底上的低k电介质支撑层的上侧和下侧，使得在衬底上空间效率最大化。 低k电介质支撑层提供电感器和电容器之间的支撑，使得衬底损耗最小化并且电感器的Q因数增强。

公开(公告)号：US20060273444A1

公开(公告)日：2006-12-07

申请号：US11390220

申请日：2006-03-28

Applicant: Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

Inventor： Kyu-dong Jung ,  Woon-bae Kim ,  In-sang Song ,  Moon-chul Lee ,  Jun-sik Hwang ,  Suk-jin Ham

IPC: H01L23/48

CPC classification number: H01L23/055 ,  H01L23/04 ,  H01L27/14618 ,  H01L2224/16

Abstract: A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.

Abstract translation: 提供电路模块封装的封装芯片和封装电路模块的方法。 包装芯片包括基底晶片; 基底晶片上的电路模块; 封装晶片，其具有空腔并与所述基底晶片组合，使得所述电路模块装配在所述腔内; 连接所述空腔的上表面和下表面的连接电极; 以及连接电极和封装晶片之间的晶种层。 该方法包括蚀刻封装晶片的下表面以形成空腔，在下表面的区域中堆叠金属层，将基底晶片与封装晶片组合，抛光封装晶片，通过封装晶片形成通孔， 将种子层堆叠在包装晶片上，电镀通孔内部，去除种子层并形成电极。

公开(公告)号：US20060018801A1

公开(公告)日：2006-01-26

申请号：US11188000

申请日：2005-07-25

Applicant: Tae-sik Park ,  Sung-hee Lee ,  Jung-ho Kang ,  Young-il Kim ,  Moon-chul Lee

Inventor： Tae-sik Park ,  Sung-hee Lee ,  Jung-ho Kang ,  Young-il Kim ,  Moon-chul Lee

IPC: B01L3/00

CPC classification number: B01L3/50273 ,  B01L3/502715 ,  B01L2200/10 ,  B01L2300/049 ,  B01L2400/049 ,  B01L2400/06

Abstract: A bio sample processing apparatus and method using vacuum chambers in which a bio sample is injected into a first vacuum chamber connected with one end of a bio processor and, after processing, is ejected into a second vacuum chamber connected with the other end of the bio processor. The vacuum chambers and bio processor are connected with each other to form an environment with a pressure lower than atmospheric pressure, and the bio sample moves toward the second vacuum chamber due to the pressure difference created by the injection of the bio sample into the first vacuum chamber.

Abstract translation: 一种使用真空室的生物样品处理装置和方法，其中将生物样品注入与生物处理器的一端连接的第一真空室中，并且在处理之后被喷射到与生物的另一端连接的第二真空室中 处理器。 真空室和生物处理器彼此连接以形成压力低于大气压的环境，并且生物样品由于将生物样品注入第一真空产生的压差而向第二真空室移动 房间。