公开(公告)号：US20240363676A1

公开(公告)日：2024-10-31

申请号：US18767205

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Cheng CHEN ,  Wei-Li HUANG ,  Chun-Yi WU ,  Kuang-Yi WU ,  Hon-Lin HUANG ,  Chih-Hung SU ,  Chin-Yu KU ,  Chen-Shien CHEN

IPC: H01F41/04 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L28/10 ,  H01F41/046 ,  H01L21/76823 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/53204 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The magnetic element has multiple sub-layers, and each sub-layer is wider than another sub-layer above it. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element, and the isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.

公开(公告)号：US12132074B2

公开(公告)日：2024-10-29

申请号：US18306222

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wen-Shiang Liao ,  Chih-Hang Tung

IPC: H01L23/495 ,  H01F27/24 ,  H01F27/28 ,  H01F41/04 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L28/10 ,  H01F27/24 ,  H01F27/2804 ,  H01F41/041 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01F2027/2809 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/95001 ,  H01L2924/1427 ,  H01L2924/19042

Abstract: A package includes a first redistribution structure, a second redistribution structure, an inductor, a permalloy core, and a die. The second redistribution structure is over the first redistribution structure. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure, the third portion is embedded in the second redistribution structure, and the second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor. The die is disposed adjacent to the second portion of the inductor.

公开(公告)号：US12125713B2

公开(公告)日：2024-10-22

申请号：US17655832

申请日：2022-03-22

Applicant: Ferric Inc.

Inventor： Michael Lekas ,  Salahuddin Raju ,  Noah Sturcken ,  Ryan Davies ,  Denis Shishkov

IPC: H01L21/3205 ,  H01F17/00 ,  H01F41/32 ,  H01L21/02 ,  H01L21/324 ,  H01L21/78 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L21/3205 ,  H01F41/32 ,  H01L21/02172 ,  H01L21/324 ,  H01L21/7806 ,  H01L23/5227 ,  H01F17/0033 ,  H01L28/10

Abstract: A method for manufacturing a ferromagnetic-dielectric composite material comprises: (a) placing patterned ferromagnetic layer regions, in a patterning substrate assembly that includes a patterning substrate and a first dielectric layer, in physical contact with a second dielectric layer, the second dielectric layer in a receiving substrate assembly that includes a receiving substrate, (b) forming a bond between the patterned ferromagnetic layer regions and the second dielectric layer; (c) releasing the patterning substrate from the patterning substrate assembly to transfer the patterned ferromagnetic layer regions and the first dielectric layer from the patterning substrate assembly to the receiving substrate assembly; and (d) releasing the receiving substrate from the receiving substrate assembly to form the ferromagnetic-dielectric composite material.

公开(公告)号：US12113095B2

公开(公告)日：2024-10-08

申请号：US17205805

申请日：2021-03-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiaowei Zou ,  Chengbo Qiu ,  Haisheng Lu

IPC: H01F27/28 ,  H01F5/00 ,  H01L49/02

CPC classification number: H01L28/10 ,  H01F5/003 ,  H01F27/28

Abstract: This application discloses a planar inductor. The planar inductor includes a first inductor module and a second inductor module that are connected in parallel. A direction of a magnetic line of the first inductor module is opposite to a direction of a magnetic line of the second inductor module, so that the magnetic lines can form a self-close loop in the planar inductor, and impact of a far magnetic field generated by the inductor on the outside, especially a nearby inductor, can be greatly reduced, thereby reducing crosstalk between the inductors, that is, reducing a phase noise, and increasing a Q value of the inductor. In addition, this application further provides a semiconductor chip that includes the planar inductor.

公开(公告)号：US20240312692A1

公开(公告)日：2024-09-19

申请号：US18674351

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Sung Huang ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Hung-Yi Kuo ,  Ming Hung Tseng

IPC: H01F27/28 ,  H01F17/00 ,  H01F38/14 ,  H01F41/04 ,  H01F41/10 ,  H02J50/10 ,  H02J50/80

CPC classification number: H01F27/2804 ,  H01F38/14 ,  H01F41/041 ,  H01F41/10 ,  H01L28/10 ,  H02J50/10 ,  H02J50/80 ,  H01F2017/0086

Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.

公开(公告)号：US12087808B2

公开(公告)日：2024-09-10

申请号：US16942078

申请日：2020-07-29

Applicant: Silicon Laboratories Inc.

Inventor： Eduardo Jose Dos Santos Viegas

IPC: H01F27/28 ,  G06F30/398 ,  H01F41/04 ,  H01L23/58 ,  H01L49/02 ,  H05K1/16

CPC classification number: H01L28/10 ,  G06F30/398 ,  H01F27/2804 ,  H01F41/041 ,  H01L23/585 ,  H05K1/165

Abstract: In one aspect, an inductor may include at least one loop formed on a first metal layer and a non-uniform introduced pattern formed on the first metal layer and circumscribed by the at least one loop. The non-uniform introduced pattern may be formed of a plurality of structures and may have a maximum density at an interior portion thereof and a minimum density at a peripheral portion thereof, where at least some of the plurality of structures have different sizes.

公开(公告)号：US20240290691A1

公开(公告)日：2024-08-29

申请号：US18341529

申请日：2023-06-26

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Min-Han CHUANG ,  Ho-Chuan LIN ,  Chia-Chu LAI

IPC: H01L23/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L28/10 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2924/19042

Abstract: An electronic package and a manufacturing method thereof are provided, in which a magnetically permeable member and a plurality of supporting members having conductive through vias are disposed on a carrier structure having a circuit layer, the magnetically permeable member is located between two supporting members, and a conductive member is disposed on the supporting members to cover the magnetically permeable member, so that the circuit layer, the conductive through vias and the conductive member form a coil surrounding the magnetically permeable member to increase the inductance.

公开(公告)号：US12074100B2

公开(公告)日：2024-08-27

申请号：US17131222

申请日：2020-12-22

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Maiden Grace Maming

IPC: H01L23/495 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01L23/49589 ,  H01L23/49548 ,  H01L23/647 ,  H01L23/49575 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US20240274550A1

公开(公告)日：2024-08-15

申请号：US18641571

申请日：2024-04-22

Applicant: Texas Instruments Incorporated

Inventor： Michael Lee Dawson ,  Edward J. Pryor, III ,  Jeffrey L. Large ,  Mary Coles

IPC: H01L23/64 ,  H01L23/66 ,  H01Q1/22

CPC classification number: H01L23/645 ,  H01L23/66 ,  H01L28/10 ,  H01Q1/2283

Abstract: A method of fabricating a circuit package includes mounting a micro-wire for transport, the micro-wire being formed of a metal and having a diameter of 10 microns or less and introducing the mounted micro-wire and the circuit package into a focused ion beam (FIB) apparatus that comprises a FIB microscope and a nanopositioner. The method further includes: bringing the micro-wire, the nanopositioner and the circuit package into a work area for the FIB apparatus; using the nanopositioner to bring the micro-wire and the circuit package together at a location for attachment; welding the micro-wire into position; and releasing the micro-wire.

公开(公告)号：US20240234303A9

公开(公告)日：2024-07-11

申请号：US17972975

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Telesphor Kamgaing ,  Chee Kheong Yoon ,  Chu Aun Lim ,  Eng Huat Goh ,  Jooi Wah Wong ,  Kavitha Nagarajan

IPC: H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L28/10

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.