公开(公告)号：US09853122B2

公开(公告)日：2017-12-26

申请号：US15097328

申请日：2016-04-13

Applicant: LAPIS SEMICONDUCTOR CO., LTD.

Inventor： Masataka Yoshinari

IPC: H01L21/304 ,  H01L29/66 ,  H01L29/36 ,  H01L21/265 ,  H01L29/739 ,  H01L29/49 ,  H01L21/324 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L21/463 ,  H01L21/268

CPC classification number: H01L29/66348 ,  H01L21/02016 ,  H01L21/0209 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/304 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/463 ,  H01L29/36 ,  H01L29/4916 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7813 ,  Y10S438/977

Abstract: A method of fabricating a semiconductor device includes forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.

公开(公告)号：US09837578B2

公开(公告)日：2017-12-05

申请号：US14974991

申请日：2015-12-18

Applicant: LG INNOTEK CO., LTD. ,  LG ELECTRONICS INC.

Inventor： Hyun Kyong Cho ,  Sun Kyung Kim ,  Jun Ho Jang

IPC: H01L33/20 ,  H01L33/40 ,  H01L33/42 ,  H01L33/48 ,  H01L33/62 ,  H01L33/60 ,  H01L33/00 ,  H01L33/22 ,  H01L33/44

CPC classification number: H01L33/20 ,  H01L33/0079 ,  H01L33/22 ,  H01L33/405 ,  H01L33/42 ,  H01L33/44 ,  H01L33/48 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2933/0016 ,  H01L2933/0033 ,  H01L2933/0083 ,  Y10S438/977 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light emitting device including a support layer; a reflective electrode disposed on the support layer; an ohmic electrode disposed on the reflective electrode, the ohmic electrode including a transparent electrode; and a semiconductor structure disposed on the ohmic electrode, the semiconductor structure including a p-type semiconductor layer disposed on the ohmic electrode; a light emitting layer disposed on the p-type semiconductor layer; and an n-type semiconductor layer disposed on the light emitting layer. Further, the transparent electrode has a thickness in the range of 40 nm to 90 nm.

公开(公告)号：US20170170132A1

公开(公告)日：2017-06-15

申请号：US15385545

申请日：2016-12-20

Applicant: ZIPTRONIX, INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, JR.

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

公开(公告)号：US20160308333A1

公开(公告)日：2016-10-20

申请号：US15186932

申请日：2016-06-20

Applicant: Sony Corporation

Inventor： Osamu Maeda ,  Masaki Shiozaki ,  Takahiro Arakida

IPC: H01S5/42 ,  H01S5/042 ,  H01S5/02 ,  H01S5/343 ,  H01S5/187 ,  H01S5/183

CPC classification number: H01S5/423 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01S5/0217 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/042 ,  H01S5/0425 ,  H01S5/18311 ,  H01S5/18341 ,  H01S5/1838 ,  H01S5/187 ,  H01S5/34313 ,  H01S2304/04 ,  Y10S438/977

Abstract: A method of manufacturing a laser diode array capable of inhibiting electric cross talk is provided. The method of manufacturing a laser diode array includes a processing step of forming a peel layer containing an oxidizable material and a vertical resonator structure over a first substrate sequentially from the first substrate side by crystal growth, and then selectively etching the peel layer and the vertical resonator structure to the first substrate, thereby processing into a columnar shape, a peeling step of oxidizing the peel layer from a side face, and then peeling the vertical resonator structure of columnar shape from the first substrate, and a rearrangement step of jointing a plurality of vertical resonator structures of columnar shape obtained by the peeling step to a surface of a metal layer of a second substrate formed with the metal layer on the surface.

Abstract translation: 提供一种制造能够抑制串扰的激光二极管阵列的方法。 制造激光二极管阵列的方法包括以下步骤：通过晶体生长从第一衬底侧顺序地在第一衬底上形成含有可氧化材料和垂直谐振器结构的剥离层，然后选择性地蚀刻剥离层和垂直 谐振器结构，从而处理成柱状，从侧面氧化剥离层的剥离步骤，然后从第一基板剥离柱状的垂直共振器结构，以及重新连接步骤，连接多个 将通过剥离步骤获得的柱状垂直共振器结构施加到在表面上形成有金属层的第二基板的金属层的表面上。

公开(公告)号：US20160190093A1

公开(公告)日：2016-06-30

申请号：US15064467

申请日：2016-03-08

Applicant: ZIPTRONIX, INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, JR.

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

Abstract: A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract translation: 一种方法可以包括将具有衬底的半导体器件直接接合到元件的步骤; 以及去除所述衬底的一部分以在结合之后露出所述半导体器件的剩余部分。 元件可以包括用于热扩散，阻抗匹配或RF隔离的衬底之一，天线以及由无源元件组成的匹配网络。 第二热扩散基板可以结合到半导体器件的其余部分。 互连可以通过第一或第二基底进行。 该方法还可以包括将多个半导体器件接合到元件，并且元件可以具有设置半导体器件的凹部。

公开(公告)号：US09159605B2

公开(公告)日：2015-10-13

申请号：US14471583

申请日：2014-08-28

Applicant: Silicon Genesis Corporation

Inventor： Francois J. Henley ,  Nathan Cheung

IPC: H01L21/46 ,  H01L21/425 ,  H01L21/762 ,  H01L21/268 ,  H01L21/18 ,  H01L21/20 ,  H01L21/78 ,  H01L21/223 ,  H01L21/304 ,  H01L21/265

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/268 ,  H01L21/304 ,  H01L21/7624 ,  H01L21/7813 ,  Y10S117/915 ,  Y10S156/93 ,  Y10S438/974 ,  Y10S438/977

Abstract: A method for forming a multi-material thin film includes providing a multi-material donor substrate comprising single crystal silicon and an overlying film comprising GaN. Energetic particles are introduced through a surface of the multi-material donor substrate to a selected depth within the single crystal silicon. The method includes providing energy to a selected region of the donor substrate to initiate a controlled cleaving action in the donor substrate. Then, a cleaving action is made using a propagating cleave front to free a multi-material film from a remaining portion of the donor substrate, the multi-material film comprising single crystal silicon and the overlying film.

Abstract translation: 一种形成多材料薄膜的方法包括提供包括单晶硅的多材料施主衬底和包含GaN的上覆膜。 能量粒子通过多材料供体衬底的表面引入单晶硅内的选定深度。 该方法包括向施主衬底的选定区域提供能量，以在施主衬底中开始受控的切割作用。 然后，使用传播劈裂前端从施主衬底的剩余部分释放多材料膜，所述多材料膜包括单晶硅和上覆膜。

公开(公告)号：US20150221741A1

公开(公告)日：2015-08-06

申请号：US14688308

申请日：2015-04-16

Applicant: LAPIS SEMICONDUCTOR CO., LTD.

Inventor： MASATAKA YOSHINARI

IPC: H01L29/49 ,  H01L29/36 ,  H01L29/739

CPC classification number: H01L29/66348 ,  H01L21/02016 ,  H01L21/0209 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/304 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/463 ,  H01L29/36 ,  H01L29/4916 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7813 ,  Y10S438/977

Abstract: There is provided a method of fabricating a semiconductor device, the method including: forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.

Abstract translation: 提供一种制造半导体器件的方法，所述方法包括：在衬底的前表面形成第一半导体区域，所述第一半导体区域包括调节在衬底的厚度方向上流动的电流的有源元件; 研磨衬底的后表面; 在研磨之后，进行用包含磷的化学溶液蚀刻基板的后表面的第一蚀刻; 在第一蚀刻之后，进行蚀刻后表面的第二蚀刻，蚀刻方法具有比第一蚀刻更低的蚀刻速率; 并且在第二蚀刻之后，通过从衬底的后表面注入杂质来形成通过其流动的第二半导体区域。

公开(公告)号：US09070604B2

公开(公告)日：2015-06-30

申请号：US11926623

申请日：2007-10-29

Applicant: Shunpei Yamazaki ,  Hisashi Ohtani

Inventor： Shunpei Yamazaki ,  Hisashi Ohtani

IPC: H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L31/112 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/062 ,  H01L31/113 ,  H01L27/12 ,  H01L21/70

CPC classification number: H01L27/1266 ,  H01L21/76243 ,  H01L21/76254 ,  H01L21/76256 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/045 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/973 ,  Y10S438/977

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

公开(公告)号：US20150132873A1

公开(公告)日：2015-05-14

申请号：US14479100

申请日：2014-09-05

Applicant: The Board of Trustees of the University of Illinois

Inventor： John A. ROGERS ,  Ralph NUZZO ,  Hoon-sik KIM ,  Eric BRUECKNER ,  Sang Il PARK ,  Rak Hwan KIM

IPC: H01L33/00 ,  H01L33/54 ,  H01L23/00 ,  H01L25/075 ,  H01L25/00 ,  H01L33/50 ,  H01L33/48

CPC classification number: H01L25/0753 ,  H01L21/6835 ,  H01L24/83 ,  H01L24/95 ,  H01L25/50 ,  H01L33/0079 ,  H01L33/32 ,  H01L33/486 ,  H01L33/507 ,  H01L33/54 ,  H01L33/62 ,  H01L2221/68322 ,  H01L2221/6835 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/8312 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/83874 ,  H01L2224/95085 ,  H01L2924/01322 ,  H01L2924/05432 ,  H01L2924/06 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2933/0041 ,  H01L2933/005 ,  Y10S438/977 ,  H01L2924/00

Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.

Abstract translation: 这里描述了用于制造，组装和布置电子设备的可打印结构和方法。 本文描述的许多方法对于组装电子器件是有用的，其中一个或多个器件部件被嵌入在嵌入过程中被图案化的聚合物中，其中沟槽用于器件部件之间的电互连。 本文描述的一些方法可用于通过印刷方法组装电子装置，例如通过干式转印接触印刷方法。 本文还描述了GaN发光二极管以及用于制造和布置GaN发光二极管的方法，例如用于显示器或照明系统。

公开(公告)号：US09018031B2

公开(公告)日：2015-04-28

申请号：US14061750

申请日：2013-10-23

Applicant: Panasonic Corporation

Inventor： Akira Tsukamoto

IPC: H01L31/18 ,  H01L27/146

CPC classification number: H01L27/14689 ,  H01L27/146 ,  H01L27/14632 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L31/18 ,  H01L31/1892 ,  Y10S438/977

Abstract: A single crystal silicon layer is formed on a principal surface of a first wafer by epitaxial growth. A silicon oxide layer is formed on the single crystal silicon layer. Next, a defect layer is formed inside the single crystal silicon layer by ion implantation, and then, the second wafer is bonded to the silicon oxide layer on the first wafer. After that, an SOI wafer including the silicon oxide layer formed on the second wafer and the single crystal silicon layer formed on the silicon oxide layer is formed by separating the first wafer including the single crystal silicon layer from the second wafer including the single crystal silicon layer in the defect layer. Then, a photodiode is formed in the single crystal silicon layer. An interconnect layer is formed on a surface of the single crystal silicon layer which is opposite to the silicon oxide layer.

Abstract translation: 通过外延生长在第一晶片的主表面上形成单晶硅层。 在单晶硅层上形成氧化硅层。 接下来，通过离子注入在单晶硅层内形成缺陷层，然后将第二晶片接合到第一晶片上的氧化硅层。 之后，通过将包括单晶硅层的第一晶片与包括单晶硅的第二晶片分离，形成包括形成在第二晶片上的氧化硅层和形成在氧化硅层上的单晶硅层的SOI晶片 层在缺陷层。 然后，在单晶硅层中形成光电二极管。 在与硅氧化物层相反的单晶硅层的表面上形成互连层。