公开(公告)号：US06718523B2

公开(公告)日：2004-04-06

申请号：US09899413

申请日：2001-07-05

申请人： David J. Hathaway ,  Jeffrey P. Soreff ,  Neil R. Vanderschaaf ,  James D. Warnock

发明人： David J. Hathaway ,  Jeffrey P. Soreff ,  Neil R. Vanderschaaf ,  James D. Warnock

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A method for analyzing a gated clock design in which a disabling clock gating transition prevents an output transition from occurring, assuring that no clock glitching occurs. Delays and slews are computed so that the arrival time computation that includes clock and gate signal delays are computed at the output, providing tests which ensure that no glitch situation occurs. The delays and slews are computed using a static timing analysis, which includes situations such as a late and early arriving gate clock signals. The invention may be used in any static timing analysis test to ensure that a first transition on one input of a circuit prevents the propagation of a second transition on another input of the circuit.

摘要翻译： 一种用于分析门禁时钟设计的方法，其中禁用时钟选通转换阻止发生输出转换，确保不发生时钟毛刺。 计算延迟和压摆，使得在输出端计算包括时钟和门信号延迟的到达时间计算，提供确保无故障情况发生的测试。 使用静态时序分析来计算延迟和压摆，包括迟到和早到达门时钟信号等情况。 本发明可用于任何静态时序分析测试，以确保电路的一个输入上的第一次转换可防止在该电路的另一个输入上传播第二个转换。

公开(公告)号：US06609228B1

公开(公告)日：2003-08-19

申请号：US09713571

申请日：2000-11-15

申请人： Paul H. Bergeron ,  Keith M. Carrig ,  Alvar A. Dean ,  Roger P. Gregor ,  David J. Hathaway ,  David E. Lackey ,  Harold E. Reindel ,  Larry Wissel

发明人： Paul H. Bergeron ,  Keith M. Carrig ,  Alvar A. Dean ,  Roger P. Gregor ,  David J. Hathaway ,  David E. Lackey ,  Harold E. Reindel ,  Larry Wissel

IPC分类号： G06F1750

CPC分类号： G06F17/5072 ,  G06F2217/78

摘要： A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.

摘要翻译： 时钟优化的方法和结构，包括根据时钟信号要求创建时钟馈电电路的初始放置; 识别所述时钟馈送电路的簇，其中每个簇包括与所述簇内的每个时钟馈送电路连接的不同的时钟信号供应装置; 改变时钟馈电电路和时钟信号供应装置之间的引脚连接，以将选定的时钟馈电电路切换到不同的簇，以减少时钟馈送电路和每个集群内的时钟信号供应装置之间的导线长度; 以及在设计约束内调整时钟馈电电路的位置，以进一步减少电线的长度。

公开(公告)号：US06557151B1

公开(公告)日：2003-04-29

申请号：US09650399

申请日：2000-08-29

申请人： Wilm E. Donath ,  David J. Hathaway

发明人： Wilm E. Donath ,  David J. Hathaway

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A method of distributed timing analysis for a network which has been partitioned into at least two partitions, with each partition being assigned to a separate timing analysis process which communicates with the other processes is provided. A depth first search is performed by the process assigned to the partition in which the node for which timing information is desired is located. When the depth first search encounters a node for which a timing value is required which is located in another partition, a request is immediately sent to the process corresponding to that partition for the required timing information. When the request for timing information from the other partition is answered, the associated node is placed in the propagation queue. Also, as a node is processed, successor nodes which have had their predecessors processed are added to the propagation queue. The nodes in the propagation queue are processed and timing values are computed. When there are no nodes in the propagation queue, global loop detection is performed. Additionally, incremental timing updates are performed when a change is made in the network.

摘要翻译： 一种分布在至少两个分区中的网络的分布式时序分析方法，其中每个分区分配给与其他进程进行通信的单独的定时分析过程。 通过分配给期望定时信息的节点所在的分区的处理来执行深度优先搜索。 当深度第一次搜索遇到位于另一个分区中需要定时值的节点时，立即将请求发送到与该分区相对应的处理所需的定时信息。 当来自其他分区的定时信息的请求被应答时，相关联的节点被放置在传播队列中。 另外，当处理节点时，将其前辈处理的后继节点添加到传播队列中。 处理传播队列中的节点并计算定时值。 当传播队列中没有节点时，执行全局环路检测。 此外，当在网络中进行更改时，会执行增量时序更新。

公开(公告)号：US06536024B1

公开(公告)日：2003-03-18

申请号：US09617908

申请日：2000-07-14

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： G06F1750

CPC分类号： G06F17/5045 ,  G06F1/10

摘要： A method for synthesizing a logic circuit that is driven by a clock signal, and that has a plurality of clock domains each having a plurality of clock sinks. A semiconductor substrate is provided. All of the plurality of clock sinks of one clock domain are placed into at least one cluster of clock sinks on the semiconductor substrate. A clock sink-density of each cluster of clock sinks is approximately equal to or greater than a clock sink density of an integrated circuit. A first portion of the plurality of clock sinks of a domain have a higher sink density than a second portion of the plurality of clock sinks of the same domain. The first portion has a subregion and the second portion has a subregion. The subregion of the first portion is adjacent to the region of the second portion.

摘要翻译： 一种用于合成由时钟信号驱动并且具有多个时钟域的逻辑电路的方法，每个时钟域具有多个时钟信宿。 提供半导体衬底。 一个时钟域的所有多个时钟信宿被放置在半导体衬底上的至少一个时钟汇聚簇中。 每个时钟汇聚簇的时钟汇集密度近似等于或大于集成电路的时钟汇集密度。 域的多个时钟宿的第一部分具有比同一域的多个时钟汇的第二部分更高的宿密度。 第一部分具有子区域，第二部分具有子区域。 第一部分的子区域与第二部分的区域相邻。

公开(公告)号：US5944834A

公开(公告)日：1999-08-31

申请号：US938659

申请日：1997-09-26

申请人： David J. Hathaway

发明人： David J. Hathaway

IPC分类号： G06F17/50 ,  H03L7/06 ,  G06F3/00

CPC分类号： H03L7/06 ,  G06F17/5031

摘要： A method of analyzing timing differences for common path pessimism removal for a circuit containing a locked loop which controls at least two legs of a clock tree is provided. The method comprises the steps of computing the early and late mode delays for the locked loop; computing the early and late mode delays for delay segments in the circuit; identifying delay segments in the feedback path which control the locked loop; and adjusting the early and late mode delays for the delay segments in the feedback path based upon the type of feedback control used in the circuit.

摘要翻译： 提供了一种分析用于包含控制时钟树的至少两条腿的锁定环路的电路的公共路径悲观消除的定时差异的方法。 该方法包括以下步骤：计算锁定环的早期和晚期模式延迟; 计算电路中延迟段的早期和晚期模式延迟; 识别控制锁定环路的反馈路径中的延迟段; 以及基于在电路中使用的反馈控制的类型来调整反馈路径中的延迟段的早期和晚期模式延迟。

公开(公告)号：US5636372A

公开(公告)日：1997-06-03

申请号：US316519

申请日：1994-09-30

申请人： David J. Hathaway ,  Janet P. Alvarez ,  Krishna P. Belkhale

发明人： David J. Hathaway ,  Janet P. Alvarez ,  Krishna P. Belkhale

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G06F17/50 ,  G06F17/18

CPC分类号： G01R31/318357 ,  G01R31/31727 ,  G01R31/318328 ,  G06F17/5031

摘要： A method of analyzing timing differences between arrival times of distinct signals propagating through a circuit comprising: (i) identifying a first beginning point for a first data path over which data arrival times are propagated to a data endpoint; (ii) identifying a second beginning point for a second data path to the data endpoint, and for a clock path to a clock endpoint, the endpoints constituting an endpoint pair; (iii) identifying at least one common point at which the second data path and the clock path diverge; (iv) propagating data arrival times to the data endpoint from the first and second beginning points, and tagging the data arrival times propagated along the second data path with one of the common points; (v) propagating clock arrival times to the clock endpoint from the second beginning point along the clock path, and tagging the clock arrival times with one of the common points, the data and clock arrival times constituting clock/data arrival time pairs at the endpoint pair; (vi) determining the slack at the endpoint pair for the time pairs and identifying a worst time pair causing the worst slack determination; and (vii) recomputing the slack at the endpoint pair for the worst time pair, if the data arrival time in the worst time pair is tagged with the same common point, by eliminating slack caused by data and clock arrival time propagation on a shared portion of the second data path and the clock path between the second beginning point and the same common point.

摘要翻译： 一种分析通过电路传播的不同信号的到达时间之间的定时差异的方法，包括：（i）识别数据到达时间传播到数据端点的第一数据路径的第一起始点; （ii）识别到数据端点的第二数据路径的第二起始点以及针对时钟端点的时钟路径，构成端点对的端点; （iii）识别第二数据路径和时钟路径发散的至少一个公共点; （iv）从第一和第二起点将数据到达时间传播到数据端点，并用一个公共点标记沿着第二数据路径传播的数据到达时间; （v）沿着时钟路径从第二起始点将时钟到达时间传播到时钟端点，并且使用公共点之一标记时钟到达时间，在端点处构成时钟/数据到达时间对的数据和时钟到达时间 对; （vi）确定时间对的端点对处的松弛，并且识别导致最差松弛确定的最差时间对; 并且（vii）如果在最差时间对中的数据到达时间被标记有相同的公共点，则通过消除由数据引起的松弛和在共享部分上的时钟到达时间传播来重新计算端对点处的最差时间对的松弛 的第二数据路径和第二起始点和相同公共点之间的时钟路径。

公开(公告)号：US5282147A

公开(公告)日：1994-01-25

申请号：US739923

申请日：1991-08-02

申请人： John W. Goetz ,  David J. Hathaway

发明人： John W. Goetz ,  David J. Hathaway

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/505

摘要： A system for optimizing a logic network including expressing the logic network as an original graph having vertices, edges which connect the vertices and which represent connections in the logic network, and inversion markings for representing inverters in the logic network; determining a fundamental cycle(s) in the original graph; sorting the determined fundamental cycle(s) according to its parity; forming a final graph by processing the fundamental cycle(s) so as to optimize inverter placement therein while maintaining the parity thereof; comparing the inversion markings of the original and final graphs to determine a set of transformation locations in the logic network; and re-configuring the logic network in accordance with the determined transformation locations.

摘要翻译： 一种用于优化逻辑网络的系统，包括将逻辑网络表示为具有顶点的原始图形，连接顶点的边缘并且表示逻辑网络中的连接，以及用于表示逻辑网络中的反相器的反向标记; 确定原始图表中的基本循环; 根据其平等对所确定的基本周期进行排序; 通过处理基本周期形成最终图形，以便优化其中的逆变器放置，同时保持其奇偶校验; 比较原始图和最终图的反转标记，以确定逻辑网络中的一组变换位置; 以及根据确定的转换位置重新配置逻辑网络。