公开(公告)号：US06202192B1

公开(公告)日：2001-03-13

申请号：US09004813

申请日：1998-01-09

申请人： Wilm E. Donath ,  David J. Hathaway

发明人： Wilm E. Donath ,  David J. Hathaway

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A method of distributed timing analysis for a network which has been partitioned into at least two partitions, with each partition being assigned to a separate timing analysis process which communicates with the other processes is provided. A depth first search is performed by the process assigned to the partition in which the node for which timing information is desired is located. When the depth first search encounters a node for which a timing value is required which is located in another partition, a request is immediately sent to the process corresponding to that partition for the required timing information. When the request for timing information from the other partition is answered, the associated node is placed in the propagation queue. Also, as a node is processed, successor nodes which have had their predecessors processed are added to the propagation queue. The nodes in the propagation queue are processes and timing values are computed. When there are no nodes in the propagation queue, global loop detection is performed. Additionally, incremental timing updates are performed when a change is made in the network.

摘要翻译： 一种分布在至少两个分区中的网络的分布式时序分析方法，其中每个分区分配给与其他进程进行通信的单独的定时分析过程。 通过分配给期望定时信息的节点所在的分区的处理来执行深度优先搜索。 当深度第一次搜索遇到位于另一个分区中需要定时值的节点时，立即将请求发送到与该分区相对应的处理所需的定时信息。 当来自其他分区的定时信息的请求被应答时，相关联的节点被放置在传播队列中。 另外，当处理节点时，将其前辈处理的后继节点添加到传播队列中。 传播队列中的节点是进程，计算定时值。 当传播队列中没有节点时，执行全局环路检测。 此外，当在网络中进行更改时，会执行增量时序更新。

公开(公告)号：US06557151B1

公开(公告)日：2003-04-29

申请号：US09650399

申请日：2000-08-29

申请人： Wilm E. Donath ,  David J. Hathaway

发明人： Wilm E. Donath ,  David J. Hathaway

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A method of distributed timing analysis for a network which has been partitioned into at least two partitions, with each partition being assigned to a separate timing analysis process which communicates with the other processes is provided. A depth first search is performed by the process assigned to the partition in which the node for which timing information is desired is located. When the depth first search encounters a node for which a timing value is required which is located in another partition, a request is immediately sent to the process corresponding to that partition for the required timing information. When the request for timing information from the other partition is answered, the associated node is placed in the propagation queue. Also, as a node is processed, successor nodes which have had their predecessors processed are added to the propagation queue. The nodes in the propagation queue are processed and timing values are computed. When there are no nodes in the propagation queue, global loop detection is performed. Additionally, incremental timing updates are performed when a change is made in the network.

摘要翻译： 一种分布在至少两个分区中的网络的分布式时序分析方法，其中每个分区分配给与其他进程进行通信的单独的定时分析过程。 通过分配给期望定时信息的节点所在的分区的处理来执行深度优先搜索。 当深度第一次搜索遇到位于另一个分区中需要定时值的节点时，立即将请求发送到与该分区相对应的处理所需的定时信息。 当来自其他分区的定时信息的请求被应答时，相关联的节点被放置在传播队列中。 另外，当处理节点时，将其前辈处理的后继节点添加到传播队列中。 处理传播队列中的节点并计算定时值。 当传播队列中没有节点时，执行全局环路检测。 此外，当在网络中进行更改时，会执行增量时序更新。

公开(公告)号：US06314547B1

公开(公告)日：2001-11-06

申请号：US09152013

申请日：1998-09-11

申请人： Wilm E. Donath ,  Prabhakar N. Kudva

发明人： Wilm E. Donath ,  Prabhakar N. Kudva

IPC分类号： G06F1900

CPC分类号： G06F17/5068

摘要： The method for improving circuit location assignment is capable of operating in the boolean, electrical and spatial (location) domains. Optimization of location assignment parameters can be performed simultaneously by determining a subset of nets or paths and generating sets of motions to improve these nets or paths. Once sets of motions have been generated, they are tested to determine the most beneficial movement for improving the given circuit parameter (e.g., wireability, timing, etc.).

摘要翻译： 用于改善电路位置分配的方法能够在布尔，电和空间（位置）域中操作。 位置分配参数的优化可以通过确定网络或路径的子集并生成运动集来改善这些网络或路径来同时执行。 一旦产生了一组运动，就对它们进行测试，以确定用于改善给定电路参数（例如，可线性，定时等）的最有利的运动。

公开(公告)号：US06738954B1

公开(公告)日：2004-05-18

申请号：US09636478

申请日：2000-08-10

申请人： Archibald J. Allen ,  Wilm E. Donath ,  Alan D. Dziedzic ,  Mark A. Lavin ,  Daniel N. Maynard ,  Dennis M. Newns ,  Gustavo E. Tellez

发明人： Archibald J. Allen ,  Wilm E. Donath ,  Alan D. Dziedzic ,  Mark A. Lavin ,  Daniel N. Maynard ,  Dennis M. Newns ,  Gustavo E. Tellez

IPC分类号： G06F1750

CPC分类号： H01L22/20 ,  G01R31/31705

摘要： A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.

摘要翻译： 一种计算具有装置形状的集成电路的制造成品率的方法包括将集成电路分为故障机构细分（每个故障机构细分包括一个或多个故障机制，并且每个故障机制包括一个或多个缺陷机构 ），将故障机制细分为每个区域的分区，预处理每个分区中的设备形状，通过对每个分区的每个故障机制和每个分区的平均故障概率的数值积分计算每个故障机制的初始平均故障数 故障机制（数值积分产生每个缺陷机制的缺陷尺寸列表，初始平均值的计算包括设置最大积分误差极限，每个缺陷尺寸的总体最大样本量， 每个故障的可允许故障mechansim），并计算最终的平均数fau 通过迭代地减少每个故障机制的初始平均故障数量的统计误差，直到统计误差低于误差极限为止，用于集成电路。

公开(公告)号：US5392221A

公开(公告)日：1995-02-21

申请号：US714027

申请日：1991-06-12

申请人： Wilm E. Donath ,  Wing K. Luk ,  Donald T. Tang

发明人： Wilm E. Donath ,  Wing K. Luk ,  Donald T. Tang

IPC分类号： H01L21/82 ,  G06F17/50 ,  H03K19/0185 ,  G06F15/60

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A method and apparatus for minimizing the total power of a logic network subject to timing constraints. The method describes a procedure to assign power and/or delay to each circuit in a logic network such that the total power is minimized and the arrival time requirement at the outputs of the logic network is met. A subset of circuits in the logic network are powered up and powered down in repeated succession in order to minimize the total power of the logic network.

摘要翻译： 一种用于使经受时序约束的逻辑网络的总功率最小化的方法和装置。 该方法描述了对逻辑网络中的每个电路分配功率和/或延迟的过程，使得总功率被最小化并且满足逻辑网络的输出处的到达时间要求。 逻辑网络中的电路子集被重新连续上电和断电，以便最小化逻辑网络的总功率。

公开(公告)号：US4263651A

公开(公告)日：1981-04-21

申请号：US40785

申请日：1979-05-21

申请人： Wilm E. Donath ,  Robert B. Hitchcock, Sr.

发明人： Wilm E. Donath ,  Robert B. Hitchcock, Sr.

IPC分类号： G06F17/50 ,  G06F15/46

CPC分类号： G06F17/5031

摘要： A method is provided which is applied to a logic block diagram, referred to as a block graph, which consists of a plurality of logic blocks interconnected by nets which carry logic signals between the logic blocks. The method is used to determine the characteristics of the given block graph, and more particularly to analyze the block graph to identify critical paths wherein logic signals must arrive at designated blocks at a critical time, and to determine whether the path delays of such critical paths are too long or too short. When critical paths are identified which have path delays that are too long or too short, the block graph can be redesigned to avoid such delays. The method includes three basic, broad steps each of which incorporates a plurality of subsidiary implementation steps. First, from the logic block graph, special blocks defined as storage elements because of their unique function are identified and classified as "level zero" elements. Second, a procedure is carried out which "levelizes" the remaining blocks in the block graph, that is, the blocks will be designated level two, level three, level four etc. in accordance with rules defined within the method. Finally, the long and short path delays, referred to as the extreme characteristics and identified by extreme values are determined for each block in level one, followed by a determination of the extreme characteristics of each block in level two, level three, etc. The extreme characteristics thus identify the critical paths within the logic block which are too long or too short so that a redesign can be made.

摘要翻译： 提供了一种应用于被称为块图的逻辑框图的方法，该逻辑框图由在逻辑块之间传送逻辑信号的网络互连的多个逻辑块组成。 该方法用于确定给定块图的特性，更具体地，分析块图以识别其中逻辑信号必须在关键时刻到达指定块的关键路径，并且确定这些关键路径的路径延迟 太长或太短 当确定具有太长或太短路径延迟的关键路径时，可以重新设计块图以避免这种延迟。 该方法包括三个基本的，广泛的步骤，每个步骤包括多个辅助实施步骤。 首先，从逻辑块图中，由于其独特的功能而定义为存储元件的特殊块被识别并分类为“零级”元素。 其次，按照方法中定义的规则，执行块平均图中剩余块“调平”的程序，即块被指定为二级，三级，四级等。 最后，对于第一级的每个块，确定被称为极值特征并由极值识别的长短路径延迟，随后确定二级，三级等各块的极限特性。 极端特征因此识别逻辑块中的关键路径太长或太短，从而可以进行重新设计。

公开(公告)号：US06274916B1

公开(公告)日：2001-08-14

申请号：US09443367

申请日：1999-11-19

申请人： Wilm E. Donath ,  Dennis M. Newns ,  Pratap C. Pattnaik

发明人： Wilm E. Donath ,  Dennis M. Newns ,  Pratap C. Pattnaik

IPC分类号： H01L3300

CPC分类号： H01L49/003

摘要： A method and structure for a field effect transistor (FET) includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate region, and a gate oxide region separating the gate region from other regions of the FET. The channel region is a Mott insulator. The gate oxide region is thicker than the channel region, and the gate oxide region includes a higher dielectric permittivity than the Mott insulator material.

摘要翻译： 场效应晶体管（FET）的方法和结构包括源极区域，漏极区域，在源极区域和漏极区域之间延伸的沟道区域，栅极区域和将栅极区域与其它区域分离的栅极氧化物区域 的FET。 通道区域是Mott绝缘体。 栅极氧化物区域比沟道区域厚，并且栅极氧化物区域具有比Mott绝缘体材料更高的介电常数。

公开(公告)号：US5365463A

公开(公告)日：1994-11-15

申请号：US631827

申请日：1990-12-21

申请人： Wilm E. Donath ,  Robert B. Hitchcock ,  Jeffrey P. Soreff

发明人： Wilm E. Donath ,  Robert B. Hitchcock ,  Jeffrey P. Soreff

IPC分类号： G01R31/28 ,  G06F11/34 ,  G06F17/50 ,  G06F19/00 ,  G06Q50/00 ,  G06F15/60

CPC分类号： G06F11/3457 ,  G06F17/5031

摘要： An apparatus and method for simulating timing performance of designs of digital machines which allows for the avoidance of lumping of correlation of correlation coefficients which may be significant to the slacks which may occur in a particular design. Delays of particular digital elements are derived by random selections from distributions of delay values based on correlations between different observed or otherwise reasonable distributions of relative delays of digital element pairs including pairs of senses of logic value transitions, pairs of technologies and pairs of packaging levels as an accuracy enhancement. Delay distributions are built up of weighted sums of other distributions and may be asymmetrical. Several computational enhancements disclosed include arrangements allowing reductions in paging (e.g. reduction in number of accesses to secondary memory). Other enhancements include application enhancements by providing generality of methodology and accommodation of large model size, further computational enhancement by providing generality of delay propagation algorithms and diagnostic enhancements by providing cycle time/yield data and allowance of re-simulation of failure modes of design performance by retaining seed values corresponding to simulated machines.

摘要翻译： 一种用于模拟数字机器设计的定时性能的装置和方法，其允许避免可能在特定设计中可能发生的松弛的相关系数的相关性的集中。 特定数字元素的延迟通过基于延迟值分布的随机选择而导出，所述随机选择是基于数字元素对的相对延迟的不同观察或合理分布之间的相关性，包括逻辑值转换，技术对和技术对以及封装等级对 精度提高。 延迟分布由其他分布的加权和构成，可能是不对称的。 公开的几种计算增强技术包括允许减少寻呼的结构（例如减少对次级存储器的访问次数）。 其他增强功能包括通过提供大型模型尺寸的一般性方法和适应性，通过提供延迟传播算法的一般性进一步的计算增强，以及通过提供周期时间/产出数据以及允许对设计性能的故障模式进行重新仿真 保留对应于模拟机器的种子值。

公开(公告)号：US5218551A

公开(公告)日：1993-06-08

申请号：US516944

申请日：1990-04-30

申请人： Bhuwan Agrawal ,  Stephen E. Bello ,  Wilm E. Donath ,  San Y. Han ,  Joseph Hutt, Jr. ,  Jerome M. Kurtzberg ,  Roger I. McMillan ,  Reini J. Norman ,  Cyril A. Price ,  Ralph W. Wilk

发明人： Bhuwan Agrawal ,  Stephen E. Bello ,  Wilm E. Donath ,  San Y. Han ,  Joseph Hutt, Jr. ,  Jerome M. Kurtzberg ,  Roger I. McMillan ,  Reini J. Norman ,  Cyril A. Price ,  Ralph W. Wilk

IPC分类号： H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/5072

摘要： The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability. Finally, the method transfers circuit assignment to logic segment and logic segment assignment to physical location information to a conventional process for final detailed circuit placement and wiring.