Subtractive dual damascene
    101.
    发明授权
    Subtractive dual damascene 失效
    扣除双镶嵌

    公开(公告)号:US5691238A

    公开(公告)日:1997-11-25

    申请号:US478321

    申请日:1995-06-07

    摘要: A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method. The resulting interconnection level structure comprises conductive lines having upwardly and downwardly projecting vias.

    摘要翻译: 一种制造导线的互连电平的方法,以及用于集成电路的绝缘和用于半导体器件的衬底载体分离的通孔的方法,其使用反向镶嵌来形成导电线和通孔。 首先使用导电线图案来完全蚀刻该层以形成导电线开口。 开口完全被导电材料填充并平坦化,使得导电材料和绝缘层的表面是共面的。 通孔图案垂直于导电线对齐,并且导电材料被除了通孔图案覆盖的区域之外的一半蚀刻通过导电线。 由此在导线的上部形成的开口用绝缘材料填充,以完成与绝缘层的下部中的导电线和层的上部中的向上突出的通孔的双镶嵌互连水平。 此外,通过从绝对层开始比正常厚约三分之一的厚度并通过将标准双镶嵌方法与上述方法组合来形成三镶嵌层。 所产生的互连级联结构包括具有向上和向下突出的通孔的导线。

    Copper pellet for reducing electromigration effects associated with a
conductive via in a semiconductor device
    102.
    发明授权
    Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device 失效
    用于减少与半导体器件中的导电通孔相关的电迁移效应的铜芯片

    公开(公告)号:US5646448A

    公开(公告)日:1997-07-08

    申请号:US699821

    申请日:1996-08-19

    摘要: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

    摘要翻译: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属颗粒。 沉淀物由沉积在通孔上的铜或金的保形层制成,以形成位于通孔中的铜或金储存器或触点。 在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。 颗粒可以通过选择性沉积或通过蚀刻保形层形成。 可以通过溅射,准直溅射,化学气相沉积(CVD),浸渍,蒸发或其它方式沉积共形层。 可以通过各向异性干蚀刻,等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。

    Simplified dual damascene process for multi-level metallization and
interconnection structure
    103.
    发明授权
    Simplified dual damascene process for multi-level metallization and interconnection structure 失效
    用于多层次金属化和互连结构的简化双镶嵌工艺

    公开(公告)号:US5635423A

    公开(公告)日:1997-06-03

    申请号:US320516

    申请日:1994-10-11

    IPC分类号: H01L21/768 H01L21/44

    摘要: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

    摘要翻译: 通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。 在一个实施例中,用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中,其间具有蚀刻停止层。 然后在第二绝缘层中形成用于沟槽的较大开口,同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。 沟槽和通孔然后同时填充导电材料。