公开(公告)号：US08569160B2

公开(公告)日：2013-10-29

申请号：US13665603

申请日：2012-10-31

Applicant: Darrell Rinerson ,  Robin Cheung

Inventor： Darrell Rinerson ,  Robin Cheung

IPC: H01L21/768

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

公开(公告)号：US20130059436A1

公开(公告)日：2013-03-07

申请号：US13665603

申请日：2012-10-31

Applicant: Darrell Rinerson ,  Robin Cheung

Inventor： Darrell Rinerson ,  Robin Cheung

IPC: H01L21/768

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

公开(公告)号：US20120315503A1

公开(公告)日：2012-12-13

申请号：US13587774

申请日：2012-08-16

Applicant: Robin Cheung ,  Wen Zhong Kong

Inventor： Robin Cheung ,  Wen Zhong Kong

IPC: B05D1/18 ,  B01J23/42 ,  B05D1/02 ,  B32B15/01

CPC classification number: C23C18/54 ,  B32B15/018 ,  Y10T428/12875

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract translation: 一种用于在金属结构上浸镀铂金的铂电镀溶液。 浸渍铂电镀溶液不含还原剂。 电镀工艺不需要电（例如电流），并且不需要电极（例如阳极和/或阴极）。 该溶液包括铂源和包括草酸的络合剂。 该解决方案能够将铂浸入金属表面，金属基材或其至少一部分是金属的结构。 所得的铂镀层包括厚度不超过300埃的连续的铂薄膜层。 该溶液可用于包括但不限于珠宝，医疗装置，电子结构，微电子结构，MEMS结构，纳米尺寸或更小结构，用于化学和/或催化反应的结构（例如，催化转化器））的电镀制品， 和不规则形状的金属表面。

公开(公告)号：US20110229734A1

公开(公告)日：2011-09-22

申请号：US12661678

申请日：2010-03-22

Applicant: Robin Cheung ,  Wen Zhong Kong

Inventor： Robin Cheung ,  Wen Zhong Kong

IPC: B32B15/01 ,  B05D1/18 ,  C23C18/42

CPC classification number: C23C18/54 ,  B32B15/018 ,  Y10T428/12875

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract translation: 一种用于在金属结构上浸镀铂金的铂电镀溶液。 浸渍铂电镀溶液不含还原剂。 电镀工艺不需要电（例如电流），并且不需要电极（例如阳极和/或阴极）。 该溶液包括铂源和包括草酸的络合剂。 该解决方案能够将铂浸入金属表面，金属基材或其至少一部分是金属的结构。 所得的铂镀层包括厚度不超过300埃的连续的铂薄膜层。 该溶液可用于包括但不限于珠宝，医疗装置，电子结构，微电子结构，MEMS结构，纳米尺寸或更小结构，用于化学和/或催化反应的结构（例如，催化转化器））的电镀制品， 和不规则形状的金属表面。

公开(公告)号：US08003511B2

公开(公告)日：2011-08-23

申请号：US12653851

申请日：2009-12-18

Applicant: Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

Inventor： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

IPC: H01L21/44

CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US20100159688A1

公开(公告)日：2010-06-24

申请号：US12454322

申请日：2009-05-15

Applicant: Darrell Rinerson ,  Robin Cheung

Inventor： Darrell Rinerson ,  Robin Cheung

IPC: H01L21/768

CPC classification number: G11C13/0026 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/24 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

Abstract: Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

Abstract translation: 公开了器件制造，包括在第一制造设备处形成器件的第一部分，作为前端（FEOL）工艺的一部分，器件的第一部分包括通过FEOL处理形成的基底晶片 ，并且随后在第二制造设施处执行一个或多个后端（BEOL）处理以形成IC，所述一个或多个BEOL处理包括完成所述设备的形成（例如，包括存储器的IC ）通过在基底晶片上沉积一个或多个存储层。 可以使用FEOL处理来形成有源电路管芯（例如，Si晶片上的CMOS电路），并且BEOL处理可用于形成在每个有源电路管芯的顶部上，由薄膜形成的一层或多层交叉点存储器阵列 可能或可能不与某些或全部FEOL流程兼容或相同的处理技术。

公开(公告)号：US20090156012A1

公开(公告)日：2009-06-18

申请号：US11954550

申请日：2007-12-12

Applicant: CHANG-LIN HSIEH ,  BINXI GU ,  JIE YUAN ,  HUI XIONG DAI ,  ROBIN CHEUNG ,  SUBHASH DESHMUKH

Inventor： CHANG-LIN HSIEH ,  BINXI GU ,  JIE YUAN ,  HUI XIONG DAI ,  ROBIN CHEUNG ,  SUBHASH DESHMUKH

IPC: H01L21/461

CPC classification number: H01L21/76808 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

Abstract: Methods for forming dual damascene structures in low-k dielectric materials that facilitate reducing photoresist poison issues are provided herein. In some embodiments, such methods may include plasma etching a via through a first mask layer into a low-k dielectric material disposed on a substrate. The first mask layer may then be removed using a process including exposing the first mask layer to a first plasma comprising an oxygen containing gas and at least one of a dilutant gas or a passivation gas, and subsequently exposing the first mask layer to a second plasma comprising an oxygen containing gas and formed using one of either plasma bias power or plasma source power. An anti-reflective coating may then be deposited into the via and atop the low-k dielectric material. A trench may then be plasma etched through a second mask layer formed atop the anti-reflective coating into the low-k dielectric material.

Abstract translation: 本文提供了在低k电介质材料中形成双重镶嵌结构的方法，其有助于减少光致抗蚀剂的毒性问题。 在一些实施例中，这样的方法可以包括将通过第一掩模层的通孔等离子体蚀刻到设置在基板上的低k电介质材料。 然后可以使用包括将第一掩模层暴露于包含含氧气体和稀释气体或钝化气体中的至少一种的第一等离子体的方法去除第一掩模层，并随后将第一掩模层暴露于第二等离子体 包括含氧气体并且使用等离子体偏置功率或等离子体源功率之一来形成。 然后可以将抗反射涂层沉积到低k电介质材料的通孔中。 然后可以通过在抗反射涂层顶部形成低k电介质材料的第二掩模层等离子体蚀刻沟槽。

公开(公告)号：US06842659B2

公开(公告)日：2005-01-11

申请号：US09939073

申请日：2001-08-24

Applicant: Suketu Parikh ,  Robin Cheung

Inventor： Suketu Parikh ,  Robin Cheung

IPC: G05B19/418 ,  H01L21/66 ,  G06F19/00

CPC classification number: H01L22/20 ,  G05B19/4187 ,  G05B19/41875 ,  G05B2219/32179 ,  G05B2219/32182 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/205 ,  Y02P90/22

Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer. As such, the output of the metrology data analyzer provides control parameters to process controllers connected controllers connected to each of the tools within the semiconductor wafer processing system. Consequently, the operation of the metrology stations and the metrology data analyzer provides both feed forward and feed back data to control the tools based upon certain information that is gathered within the metrology station.

Abstract translation: 一种用于在多步骤处理系统内执行工具内监控和控制的方法和装置。 该方法通过独立操作处理工具处理工件来监视工件的处理，并为各种独立操作的加工工具生成控制参数，以优化工件的加工。 更具体地，该设备提供位于多个半导体晶片处理工具中的每一个之间的计量站，使得当它们从一个工具传递到另一个工具提供内部工具监视时，可以对晶片进行测量。 由计量站收集的数据耦合到度量数据分析器，该测量数据分析器确定是否应该调整多个晶片处理工具中的任何一个以改善整个晶片的处理。 因此，测量数据分析仪的输出提供控制参数以处理连接到半导体晶片处理系统内的每个工具的控制器连接的控制器。 因此，计量站和度量数据分析仪的操作提供前馈和反馈数据，以基于在计量站内收集的某些信息来控制工具。

公开(公告)号：US06818066B2

公开(公告)日：2004-11-16

申请号：US09850841

申请日：2001-05-07

Applicant: Robin Cheung

Inventor： Robin Cheung

IPC: C23C880

CPC classification number: H01L21/76849 ,  H01L21/288 ,  Y10S134/902

Abstract: A system and method for treating a substrate by integrating the annealing of a metal-containing layer on a substrate as part of a chemical mechanical polishing process. In one embodiment, a system for treating a substrate generally includes an annealing station incorporated into a chemical mechanical polishing processing system that includes a deposition station utilized to form a metal-containing layer on the substrate.

Abstract translation: 作为化学机械抛光工艺的一部分，通过将基板上的含金属层的退火结合在一起来处理基板的系统和方法。 在一个实施例中，用于处理衬底的系统通常包括结合到化学机械抛光处理系统中的退火站，其包括用于在衬底上形成含金属层的沉积站。

公开(公告)号：US06477787B2

公开(公告)日：2002-11-12

申请号：US10073762

申请日：2002-02-11

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: F26B700

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.