公开(公告)号：US08035153B2

公开(公告)日：2011-10-11

申请号：US12788177

申请日：2010-05-26

Applicant: Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

Inventor： Shenqing Fang ,  Jihwan Choi ,  Calvin Gabriel ,  Fei Wang ,  Angela Hui ,  Alexander Nickel ,  Zubin Patel ,  Phillip Jones ,  Mark Chang ,  Minh-Van Ngo

IPC: H01L29/788

CPC classification number: H01L21/28282 ,  H01L27/11568

Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

Abstract translation: 公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。 在本发明中，在电荷俘获层上沉积非保形膜，以在芯源极/漏极区域的顶部形成厚膜，并在STI沟槽顶部形成夹断和空隙或窄通道。 在非保形膜上进行蚀刻以打开夹断或在非保形状态下加宽窄通道。 然后在核心单元之间完全或部分蚀刻捕获层。 去除非保形膜。 并形成顶部氧化物。 如果捕获层被部分蚀刻，则顶部氧化物将剩余的陷阱层转化为氧化物，并且因此隔离陷阱层。

公开(公告)号：US20100099249A1

公开(公告)日：2010-04-22

申请号：US12644457

申请日：2009-12-22

Applicant: Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

Inventor： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC: H01L21/285 ,  H01L21/3205

CPC classification number: H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract translation: 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US07691751B2

公开(公告)日：2010-04-06

申请号：US11924823

申请日：2007-10-26

Applicant: Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

Inventor： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC: H01L21/4763

CPC classification number: H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract translation: 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US20080061359A1

公开(公告)日：2008-03-13

申请号：US11702847

申请日：2007-02-05

Applicant: Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

Inventor： Chungho Lee ,  Hiroyuki Kinoshita ,  Zoran Krivokapic ,  Wei Zheng ,  Mark Chang ,  Rinji Sugino ,  Chi Chang

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7885 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a stack formed over a substrate. The stack includes a gate oxide layer and an overlying polycrystalline silicon layer. The stack further includes first and second undercut regions formed under the polycrystalline silicon layer and adjacent to the gate oxide layer. The memory cell further includes a first charge storage element formed in the first undercut region and a second charge storage element formed in the second undercut region.

Abstract translation: 本发明的实施例涉及存储单元。 存储单元包括形成在衬底上的堆叠。 堆叠包括栅极氧化物层和上覆的多晶硅层。 堆叠还包括形成在多晶硅层下方并与栅极氧化物层相邻的第一和第二底切区域。 存储单元还包括形成在第一底切区域中的第一电荷存储元件和形成在第二底切区域中的第二电荷存储元件。

公开(公告)号：US20050045877A1

公开(公告)日：2005-03-03

申请号：US10951370

申请日：2004-09-28

Applicant: Christopher Lyons ,  Ramkumar Subramanian ,  Mark Chang

Inventor： Christopher Lyons ,  Ramkumar Subramanian ,  Mark Chang

IPC: G11C11/56 ,  G11C13/02 ,  H01L27/28 ,  H01L51/00

CPC classification number: H01L27/285 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C13/04 ,  Y10S977/943

Abstract: A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.

Abstract translation: 公开了一种由在两个电极之间具有可控导电介质的两个电极制成的有机存储单元的方法。 可控导电介质包含含有光敏化合物的有机半导体层。 使用图案化技术将有机半导体层形成为存储单元。

公开(公告)号：US06486029B1

公开(公告)日：2002-11-26

申请号：US09627563

申请日：2000-07-28

Applicant: David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

Inventor： David K. Foote ,  Bharath Rangarajan ,  Stephan K. Park ,  Fei Wang ,  Dawn M. Hopper ,  Jack Thomas ,  Mark Chang ,  Mark Ramsbey

IPC: H01L218247

CPC classification number: H01L27/11568 ,  H01L27/115 ,  Y10S438/954

Abstract: A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. Preferably, the hard mask includes a material selected from the group consisting of tungsten, titanium, titanium nitride, polysilicon, silicon, silicon nitride, silicon oxi-nitride, and silicon rich nitride. In one preferred embodiment, the process further includes implanting the semiconductor substrate with a p-type dopant at an angle substantially normal to the principal surface of the semiconductor substrate and annealing the semiconductor substrate upon implanting the semiconductor substrate with a p-type dopant. In one preferred embodiment, the process further includes implanting the semiconductor substrate with an n-type dopant.

Abstract translation: 一种用于在2位EEPROM器件中制造存储单元的工艺，该工艺包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。 优选地，硬掩模包括选自钨，钛，氮化钛，多晶硅，硅，氮化硅，氧化氮化硅和富氮的氮化物的材料。 在一个优选实施例中，该方法还包括以基本上垂直于半导体衬底的主表面的角度注入具有p型掺杂剂的半导体衬底，并在用p型掺杂剂注入半导体衬底时退火半导体衬底。 在一个优选实施例中，该工艺还包括用n型掺杂剂注入半导体衬底。

公开(公告)号：US08935110B2

公开(公告)日：2015-01-13

申请号：US13125794

申请日：2009-10-26

Applicant: Mark Chang-Ming Hsieh ,  David Russell Anderson

Inventor： Mark Chang-Ming Hsieh ,  David Russell Anderson

IPC: G01R21/00 ,  F22B35/00 ,  F24H3/00 ,  F24D19/10

CPC classification number: F24D19/1009

Abstract: A system for analyzing an interior energy system including: at least one detachable sensor arranged to monitor a portion of the interior energy system; and an apparatus including a processor configured to receive data of a first parameter of the interior energy system from the at least one detachable sensor and determine a second parameter of the interior energy which is inferred on the basis of the received data of the first parameter; and determine a characteristic of the interior energy system from the determined second parameter. The system may provide analysis of the interior energy system and recommend improvements.

Abstract translation: 一种用于分析内部能量系统的系统，包括：至少一个可拆卸的传感器，布置成监测内部能量系统的一部分; 以及包括处理器的设备，其被配置为从所述至少一个可拆卸传感器接收所述内部能量系统的第一参数的数据，并且基于所接收的所述第一参数的数据来确定所述内部能量的第二参数; 并根据确定的第二参数确定内部能量系统的特性。 该系统可以提供对内部能源系统的分析并推荐改进。

公开(公告)号：US08445372B2

公开(公告)日：2013-05-21

申请号：US12644457

申请日：2009-12-22

Applicant: Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

Inventor： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

IPC: H01L21/285 ,  H01L21/3205

CPC classification number: H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract translation: 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

公开(公告)号：US20110276288A1

公开(公告)日：2011-11-10

申请号：US13125794

申请日：2009-10-26

Applicant: Mark Chang-Ming Hsieh ,  David Russell Anderson

Inventor： Mark Chang-Ming Hsieh ,  David Russell Anderson

IPC: G06F19/00

CPC classification number: F24D19/1009

Abstract: A system for analysing an interior energy system comprising: at least one detachable sensor arranged to monitor a portion of the interior energy system; and an apparatus comprising a processor configured to receive data of a first parameter of the interior energy system from the at least one detachable sensor and determine a second parameter of the interior energy which is inferred on the basis of the received data of the first parameter; and determine a characteristic of the interior energy system from the determined second parameter. The system may provide analysis of the interior energy system and recommend improvements.

Abstract translation: 一种用于分析内部能量系统的系统，包括：至少一个可拆卸传感器，布置成监测所述内部能量系统的一部分; 以及包括处理器的装置，其被配置为从所述至少一个可拆卸传感器接收所述内部能量系统的第一参数的数据，并且基于所述接收到的所述第一参数的数据来确定所述内部能量的第二参数; 并根据确定的第二参数确定内部能量系统的特性。 该系统可以提供对内部能源系统的分析并推荐改进。

公开(公告)号：US20110048729A1

公开(公告)日：2011-03-03

申请号：US12546794

申请日：2009-08-25

Applicant: Michael Y.H. LUO ,  Bob Lixin ZHANG ,  Shih-Hsiao Mark CHANG

Inventor： Michael Y.H. LUO ,  Bob Lixin ZHANG ,  Shih-Hsiao Mark CHANG

IPC: E21B17/01

CPC classification number: E21B19/004

Abstract: The present disclosure provides an improved design for a pull tube sleeved stress joint and associated pull tube for managing stresses on a catenary riser for a floating offshore structure. The pull tube sleeve stress joint includes at least one sleeve surrounding a length of the pull tube with an annular gap between the sleeve and pull tube and a link ring therebetween. For embodiments having a plurality of sleeves, a first sleeve can be spaced by an annular first gap from the pull tube and coupled thereto with a first ring between the pull tube and the first sleeve, and a second sleeve can be spaced by an annular second gap from the first sleeve and coupled thereto with a second ring between the first sleeve and the second sleeve. Both pull tube and sleeves can be made with regular pipe segments welded together with regular girth welds.

Abstract translation: 本公开提供了一种用于拉管套管应力接头和相关联的拉管的改进设计，用于管理用于浮动海上结构的悬链立管上的应力。 拉管套筒应力接头包括围绕拉管长度的至少一个套管，套筒和拉管之间具有环形间隙，以及在其间的连接环。 对于具有多个套筒的实施例，第一套筒可以与拉管间隔开环形的第一间隙，并且与拉管之间的第一环耦合，并且第二套筒可以间隔开一个环形的第二套筒 间隙从第一套筒并与第一套筒和第二套筒之间的第二环联接。 拉管和套管都可以用规则的管段制成，其中规则的环形焊缝焊接在一起。