利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.026 秒)

    Simplified dual damascene process for multi-level metallization and interconnection structure
    1.
    发明授权
    Simplified dual damascene process for multi-level metallization and interconnection structure 失效
    用于多层次金属化和互连结构的简化双镶嵌工艺

    公开(公告)号：US5635423A

    公开(公告)日：1997-06-03

    申请号：US320516

    申请日：1994-10-11

    申请人： Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

    发明人： Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

    摘要： A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

    摘要翻译： 通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。 在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。 然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。 沟槽和通孔然后同时填充导电材料。

    SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK
    4.
    发明申请
    SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK 有权
    选择性硅胶形成使用耐蚀蚀回填

    公开(公告)号：US20100099249A1

    公开(公告)日：2010-04-22

    申请号：US12644457

    申请日：2009-12-22

    申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    IPC分类号： H01L21/285 ,  H01L21/3205

    CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

    摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

    摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

    Selective silicide formation using resist etchback
    5.
    发明授权
    Selective silicide formation using resist etchback 有权
    使用抗蚀剂回蚀的选择性硅化物形成

    公开(公告)号：US07691751B2

    公开(公告)日：2010-04-06

    申请号：US11924823

    申请日：2007-10-26

    申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

    摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

    摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。

    Selective contact formation using masking and resist patterning techniques
    9.
    发明授权
    Selective contact formation using masking and resist patterning techniques 有权
    使用掩模和抗蚀剂图案化技术的选择性接触形成

    公开(公告)号：US07622389B1

    公开(公告)日：2009-11-24

    申请号：US11411353

    申请日：2006-04-25

    申请人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    发明人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    IPC分类号： H01L21/302

    CPC分类号： H01L27/11526 ,  H01L27/11548

    摘要： A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.

    摘要翻译： 包括选择性导电触点的半导体器件的制造方法包括在第一和第二存储器件部件上沉积抗蚀剂的步骤，第一和第二部件中的每一个包括形成在衬底中的接合部以及在接合部之间形成在衬底上的栅极。 然后将抗蚀剂从第二部件移除，从而在每个第二部件控制浇口和结上形成抗蚀剂开口。 然后蚀刻抗蚀剂，从而暴露第一组分控制栅极中的每一个，而不暴露围绕第一组分控制栅极的衬底。 然后在暴露的第一部件控制栅极和第二部件控制栅极和结上形成导电触点。

    Selective silicide formation using resist etch back
    10.
    发明授权
    Selective silicide formation using resist etch back 有权
    使用抗蚀剂回蚀的选择性硅化物形成

    公开(公告)号：US08445372B2

    公开(公告)日：2013-05-21

    申请号：US12644457

    申请日：2009-12-22

    申请人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    发明人： Kyunghoon Min ,  Angela Hui ,  Hiroyuki Kinoshita ,  Ning Cheng ,  Mark Chang

    IPC分类号： H01L21/285 ,  H01L21/3205

    CPC分类号： H01L27/115 ,  H01L21/28518 ,  H01L21/31144 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L27/11568 ,  H01L29/665

    摘要： Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

    摘要翻译： 提供了在存储器件上选择性地形成金属硅化物的方法。 所述方法可以包括在存储器件上形成掩模层; 在掩模层上形成图案化的抗蚀剂; 去除图案化抗蚀剂的上部; 通过去除未被图案化抗蚀剂覆盖的掩模层的部分来形成图案化掩模层; 以及通过形成在存储器件上的金属层与未被图案化掩模层覆盖的存储器件的部分的化学反应在存储器件上形成金属硅化物。 通过防止由图案化掩模层覆盖的存储器件的下层含硅层/部件的硅化，该方法可以选择性地在存储器件的期望部分上形成金属硅化物。