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101.发明申请Method, System and Program Product for Defining and Recording Threshold-Qualified Count Events of a Simulation By Testcases 有权方法，系统和程序产品，用于定义和记录通过测试模拟的阈值合格计数事件公开(公告)号：US20090112561A1
公开(公告)日：2009-04-30
申请号：US11930808
申请日：2007-10-31
IPC分类号： G06G7/62
CPC分类号： G06F17/5022 , G01R31/318357
摘要： A design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and the simulation includes counting occurrences of the count event in the count event counter to obtain a count event value. A threshold is also established for an aggregate count event value for the count event counter. After completion of the testcase, a determination is made whether addition of the count event value to the aggregate count event value for the count event counter would cause the aggregate count event value to exceed the threshold. If not, the count event value is recorded in a testcase data storage area, and the count event value is accumulated in the aggregate count event value. If so, the count event value is discarded without recording the count event value in the testcase data storage area.
摘要翻译： 使用硬件描述语言（HDL）仿真模型通过用测试用例来刺激HDL仿真模型来模拟设计。 HDL仿真模型包括未形成设计部分的仪器，其中包括用于设计中的计数事件的计数事件计数器，并且模拟包括计数事件计数器中的计数事件的计数以获得计数事件值。 也为计数事件计数器的聚合计数事件值建立阈值。 在测试箱完成之后，确定计数事件值对于计数事件计数器的累加计数事件值的添加是否会导致聚合计数事件值超过阈值。 如果不是，计数事件值被记录在测试用例数据存储区域中，并且计数事件值被累积在聚合计数事件值中。 如果是这样，则计数事件值被丢弃，而不在计数器数据存储区域中记录计数事件值。
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102.发明授权Method, system and program product for providing a configuration specification language supporting error checking dials 失效方法，系统和程序产品，用于提供支持错误检查拨盘的配置说明语言公开(公告)号：US07441209B2
公开(公告)日：2008-10-21
申请号：US11245300
申请日：2005-10-06
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A digital system includes one or more design entities containing a functional portion of the digital system. Within a configuration database, one or more configuration entities are instantiated. The configuration entities including an Error checking Dial (EDial) having a plurality of input latches within the digital design and a plurality of output latches within the digital design. The EDial has an associated function defining a relationship between values of the input latches and values of the output latches. An instance of the EDial in the configuration database is accessed to access the values of the output latches in the digital design.
摘要翻译： 数字系统包括包含数字系统的功能部分的一个或多个设计实体。 在配置数据库中，一个或多个配置实体被实例化。 配置实体包括在数字设计中具有多个输入锁存器的错误检查拨号（EDial）和数字设计中的多个输出锁存器。 EDial具有定义输入锁存器的值和输出锁存器值之间的关系的相关函数。 访问配置数据库中的EDial实例以访问数字设计中输出锁存器的值。
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103.发明授权Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights 有权用于指定利用拨盘偏置权重的数字系统的配置的方法，系统和程序产品公开(公告)号：US07434193B2
公开(公告)日：2008-10-07
申请号：US11345847
申请日：2006-02-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different possible input values has a different associated output value set for the one or more outputs. Each instance of the Dial entity determines a value of at least one of a plurality of configuration latches in a digital system separate from the database. The database also associates with the Dial entity at least one set of biasing weights that, when applied, determines a probability of each instance of the Dial entity having particular ones of the plurality of different possible input values. In response to a call to set the plurality of configuration latches, the database is accessed to apply the at least one set of biasing weights to select one of the plurality of different possible input values for the at least one instance of the Dial entity. The plurality of configuration latches in the digital system are set based upon the output value set for the one or more outputs of the at least one instance of the Dial entity.
摘要翻译： 在数据处理的方法中，数据库定义了Dial实体和Dial实体的至少一个实例。 Dial实体的每个实例具有具有多个不同可能输入值和一个或多个输出的输入，并且多个不同可能输入值中的每一个具有为一个或多个输出设置的不同的相关输出值。 Dial实体的每个实例确定与数据库分离的数字系统中的多个配置锁存器中的至少一个的值。 所述数据库还将所述至少一组偏置权重与所述拨号实体相关联，所述偏置权重在被应用时确定具有所述多个不同可能输入值中的特定个体的所述拨号实体的每个实例的概率。 响应于设置多个配置锁存器的呼叫，访问数据库以应用至少一组偏置权重以选择Dial实体的至少一个实例的多个不同可能输入值中的一个。 基于为Dial实体的至少一个实例的一个或多个输出设置的输出值来设置数字系统中的多个配置锁存器。
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104.发明申请PROGRAM PRODUCT SUPPORTING SPECIFICATION OF SIGNALS FOR SIMULATION RESULT VIEWING 失效支持模拟结果查询信号规范的程序产品公开(公告)号：US20080229193A1
公开(公告)日：2008-09-18
申请号：US12129813
申请日：2008-05-30
申请人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
发明人： GABOR BOBOK , Wolfgang Roesner , Derek E. Williams
IPC分类号： G06F17/00
CPC分类号： G06F17/5022
摘要： According to a method of data processing, a data set including at least one entry specifying a signal group by a predetermined signal group name is received by a data processing system. In response to receipt of the data set, the entry in the data set is processed to identify the signal group name. Signal group information associated with an event trace file containing simulation results is accessed to determine signal names of multiple signals that are members of the signal group. Simulation results from the event trace file that are associated with instances of said multiple signals are then included within a presentation of simulation results.
摘要翻译： 根据数据处理的方法，由数据处理系统接收包括由预定信号组名称指定信号组的至少一个条目的数据集。 响应于数据集的接收，处理数据集中的条目以识别信号组名称。 与包含模拟结果的事件跟踪文件相关联的信号组信息被访问以确定作为信号组成员的多个信号的信号名称。 然后将与所述多个信号的实例相关联的事件跟踪文件的仿真结果包括在仿真结果的呈现中。
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105.发明申请METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING PRINT EVENTS IN THE SIMULATION OF A DIGITAL SYSTEM 有权在数字系统仿真中支持打印事件的方法，系统和程序产品公开(公告)号：US20080183458A1
公开(公告)日：2008-07-31
申请号：US11668542
申请日：2007-01-30
申请人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
发明人： Gabor Bobok , Wolfgang Roesner , Derek E. Williams
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, one or more HDL source files describing a digital design including a plurality of hierarchically arranged design entities are received. The one or more HDL source files include one or more statements instantiating a plurality of print events within the plurality of hierarchically arranged design entities, where each print event has an associated message and at least one associated signal in the digital design. The one or more HDL source files are processed to obtain a simulation executable model including a data structure describing the plurality of print events defined for the simulation executable model and associating each of the plurality of print events with its respective associated signal.
摘要翻译： 根据模拟处理的方法，接收描述包括多个分层布置的设计实体的数字设计的一个或多个HDL源文件。 一个或多个HDL源文件包括实例化多个分层布置的设计实体中的多个打印事件的一个或多个语句，其中每个打印事件具有相关联的消息和数字设计中的至少一个相关联的信号。 处理一个或多个HDL源文件以获得模拟可执行模型，其包括描述为模拟可执行模型定义的多个打印事件的数据结构，并将多个打印事件中的每一个与其相应的相关信号相关联。
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公开(公告)号：US08296519B2
公开(公告)日：2012-10-23
申请号：US12650961
申请日：2009-12-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.
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107.发明申请SYNCHRONIZING ACCESS TO DATA IN SHARED MEMORY VIA UPPER LEVEL CACHE QUEUING 失效通过上级缓存队列同步访问共享存储器中的数据公开(公告)号：US20110161590A1
公开(公告)日：2011-06-30
申请号：US12650961
申请日：2009-12-31
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.
摘要翻译： 处理单元包括具有确定存在或不存在预留的预约逻辑的存储下位缓存和包括存储通过上级缓存，指令执行单元，负载单元的处理器核心，该负载单元响应于 由指令执行单元通过执行装载预约指令而产生的加载备用操作的上级缓存暂时缓冲加载备用操作的加载目标地址，以及指示载入预约操作被绑定到 上级缓存中的值。 如果接收到与加载保留操作的加载目标地址冲突的存储修改操作，则处理器核心将该标志设置为特定状态，并且响应于执行存储条件指令，发送关联的存储 - 如果该标志被设置为特定状态，则向低级缓存进行条件操作，并显示故障指示。
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公开(公告)号：US07835899B2
公开(公告)日：2010-11-16
申请号：US11744922
申请日：2007-05-07
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a collection of files including one or more HDL source files describing design entities collectively representing a digital design to be simulated is received. The HDL source file(s) include a statement specifying inclusion of an instrumentation entity not forming a portion of the digital design but enabling observation of its operation during simulation. The instrumentation entity includes sequential logic containing at least one storage element, where the instrumentation entity has an output signal indicative of occurrence of a simulation event. The collection of files is processed to obtain an instrumented simulation executable model. The processing includes instantiating at least one instance of each of the plurality of design entities and instantiating the instrumentation entity. The processing further includes instantiating external instrumentation logic, logically coupled to each instance of the instrumentation entity, to record occurrences of the event.
摘要翻译： 根据模拟处理的方法，收集包括一个或多个描述设计实体的HDL源文件的文件，这些HDL源文件共同表示待仿真的数字设计。 HDL源文件包括一个声明，指明包含不形成数字设计部分的仪器实体，但能够在模拟期间观察其操作。 仪器实体包括包含至少一个存储元件的顺序逻辑，其中仪器实体具有指示模拟事件发生的输出信号。 处理文件的集合以获得仪表化的模拟可执行模型。 该处理包括实例化多个设计实体中的每一个的至少一个实例并且实例化该仪器实体。 该处理还包括实例化外部仪器逻辑，逻辑上耦合到仪器实体的每个实例以记录事件的发生。
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109.发明授权Method, system and program product for selectively removing instrumentation logic from a simulation model 失效用于从仿真模型中选择性地移除仪表逻辑的方法，系统和程序产品公开(公告)号：US07552043B2
公开(公告)日：2009-06-23
申请号：US11226969
申请日：2005-09-15
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.
摘要翻译： 根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例 模拟过程中的目的。 响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除 在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。
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110.发明申请METHOD, SYSTEM AND PROGRAM PRODUCT SUPPORTING SEQUENTIAL LOGIC IN SIMULATION INSTRUMENTATION OF AN ELECTRONIC SYSTEM 失效方法，系统和程序产品支持电子系统仿真仪器中的顺序逻辑公开(公告)号：US20080281571A1
公开(公告)日：2008-11-13
申请号：US11744922
申请日：2007-05-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a collection of files including one or more HDL source files describing design entities collectively representing a digital design to be simulated is received. The HDL source file(s) include a statement specifying inclusion of an instrumentation entity not forming a portion of the digital design but enabling observation of its operation during simulation. The instrumentation entity includes sequential logic containing at least one storage element, where the instrumentation entity has an output signal indicative of occurrence of a simulation event. The collection of files is processed to obtain an instrumented simulation executable model. The processing includes instantiating at least one instance of each of the plurality of design entities and instantiating the instrumentation entity. The processing further includes instantiating external instrumentation logic, logically coupled to each instance of the instrumentation entity, to record occurrences of the event.
摘要翻译： 根据模拟处理的方法，收集包括一个或多个描述设计实体的HDL源文件的文件，这些HDL源文件共同表示待仿真的数字设计。 HDL源文件包括一个声明，指明包含不形成数字设计部分的仪器实体，但能够在模拟期间观察其操作。 仪器实体包括包含至少一个存储元件的顺序逻辑，其中仪器实体具有指示模拟事件发生的输出信号。 处理文件的集合以获得仪表化的模拟可执行模型。 该处理包括实例化多个设计实体中的每一个的至少一个实例并且实例化该仪器实体。 该处理还包括实例化外部仪器逻辑，逻辑上耦合到仪器实体的每个实例，以记录事件的发生。
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