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1.发明申请METHOD, SYSTEM AND PROGRAM PRODUCT FOR SELECTIVELY REMOVING INSTRUMENTATION LOGIC FROM A SIMULATION MODEL 审中-公开用于从模拟模型中选择性地去除仪器逻辑的方法，系统和程序产品公开(公告)号：US20080195368A1
公开(公告)日：2008-08-14
申请号：US12060717
申请日：2008-04-01
IPC分类号： G06G7/48
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.
摘要翻译： 根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例 模拟过程中的目的。 响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除 在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。
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2.发明授权Method, system and program product for selectively removing instrumentation logic from a simulation model 失效用于从仿真模型中选择性地移除仪表逻辑的方法，系统和程序产品公开(公告)号：US07552043B2
公开(公告)日：2009-06-23
申请号：US11226969
申请日：2005-09-15
CPC分类号： G06F17/5022
摘要： According to a method of simulation processing, a simulation model is received that includes a plurality of design entity instances modeling a digital system and one or more instrumentation entity instances, separate from the plurality of design entity instances, that generate instances of instrumentation events for testing purposes during simulation. In response to receiving an exclusion list identifying at least one instance of one or more instrumentation events to be removed from the simulation model, at least one instance of the one or more instrumentation events and associated logic elements are removed from the one or more instrumentation entity instances of the simulation model prior to simulation, such that a more compact simulation model is obtained.
摘要翻译： 根据模拟处理的方法，接收模拟模型，其包括建立数字系统的多个设计实体实例和与多个设计实体实例分开的一个或多个仪表实体实例，其生成用于测试的仪表事件的实例 模拟过程中的目的。 响应于接收到排除列表，其识别要从仿真模型中移除的一个或多个仪器事件的至少一个实例，所述一个或多个检测事件和相关逻辑元件的至少一个实例从所述一个或多个检测实体中移除 在模拟之前的仿真模型的实例，使得获得更紧凑的模拟模型。
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公开(公告)号：US20120317527A1
公开(公告)日：2012-12-13
申请号：US13590115
申请日：2012-08-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译： 使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。 松弛可以计算为边缘来源的早期和晚期等级之间的差异。 重量可以进一步计算为边缘的松弛和最大松弛值之间的差。 在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。 边缘和顶点权重可以重新计算下一级分区。 分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。
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公开(公告)号：US20080201128A1
公开(公告)日：2008-08-21
申请号：US11675698
申请日：2007-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.
摘要翻译： 公开了一种用于执行三元验证的方法和系统。 最初，从逻辑电路设计的二进制模型生成三元模型。 然后记录用于对三元模型进行编码的配对。 接下来，通过去除所有无效的门对配对来减少所记录的门对配对数。 对具有减少数量的门对配对的三元模型进行三进制验证。
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公开(公告)号：US07734452B2
公开(公告)日：2010-06-08
申请号：US11675698
申请日：2007-02-16
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022
摘要： A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings.
摘要翻译： 公开了一种用于执行三元验证的方法和系统。 最初，从逻辑电路设计的二进制模型生成三元模型。 然后记录用于对三元模型进行编码的配对。 接下来，通过去除所有无效的门对配对来减少所记录的门对配对数。 对具有减少数量的门对配对的三元模型进行三进制验证。
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公开(公告)号：US08555221B2
公开(公告)日：2013-10-08
申请号：US13590115
申请日：2012-08-20
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译： 使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。 松弛可以计算为边缘来源的早期和晚期等级之间的差异。 重量可以进一步计算为边缘的松弛和最大松弛值之间的差。 在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。 边缘和顶点权重可以重新计算下一级分区。 分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。
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公开(公告)号：US08327304B2
公开(公告)日：2012-12-04
申请号：US12949328
申请日：2010-11-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
摘要翻译： 使用具有作为松弛功能的边缘权重的定向超图来对电路设计进行硬件加速功能验证。 松弛可以计算为边缘来源的早期和晚期等级之间的差异。 重量可以进一步计算为边缘的松弛和最大松弛值之间的差。 在优选实施例中，每个顶点还具有与不同节点类型的资源需求相关联的多个权重，并且限制划分以防止顶点移动，其将导致基于加速器架构的给定分区的顶点权重超过分区资源容量。 边缘和顶点权重可以重新计算下一级分区。 分区过程可以重复迭代直到满足终止标准，终止标准部分地基于每个分区中的定向切割的数量。
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公开(公告)号：US20120131530A1
公开(公告)日：2012-05-24
申请号：US12949328
申请日：2010-11-18
CPC分类号： G06F17/5027
摘要： A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.
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9.发明授权Partitioning and scheduling uniform operator logic trees for hardware accelerators 失效为硬件加速器分区和调度统一运算符逻辑树公开(公告)号：US08495535B2
公开(公告)日：2013-07-23
申请号：US13305156
申请日：2011-11-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/04
摘要： A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved.
摘要翻译： 通过在保留节点信息的同时移除统一运算符树（例如，断言树）的内部门来编译用于硬件加速功能验证的电路设计，并且划分电路以优化连接性而不受统一运算符树的约束。 分区后，为分区构建子树，并聚合形成主树。 子树可以基于叶节点的等级具有不同深度的叶节点，并且主树可以基于子树的模拟深度类似地提供来自不同深度的子树的输入。 重新合成的主树在结构上与原始统一运算符树不同，但是由于输入是可交换的（例如，或门），所以保留了模型的功能等同性。
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