Abstract:
A pixel structure includes a first patterned metal layer, a gate insulating layer, a semiconductor channel layer, a second patterned metal layer, a passivation layer, and a conducting layer. A gate line of the second patterned metal layer is electrically connected by the conducting layer to a gate extension electrode of the first patterned metal layer. A source electrode of the second patterned metal layer is electrically connected by the conducting layer to a second data line segment of the first patterned metal layer. A method for fabricating a pixel structure is also disclosed herein.
Abstract:
A pixel structure including a gate, a gate dielectric layer, a patterned semiconductor layer having a channel area disposed above the gate, a patterned dielectric layer having an etching-stop layer disposed above the gate and a number of bumps, a patterned metal layer having a reflective pixel electrode, a source and a drain, an overcoat dielectric layer, and a transparent pixel electrode sequentially disposed on a substrate is provided. The source and the drain respectively cover portions of the channel area. The reflective pixel electrode connects the drain and covers the bumps to form an uneven surface. The overcoat dielectric layer disposed on a transistor constituted by the gate, the gate dielectric layer, the patterned semiconductor layer, the source and the drain has a contact opening exposing a portion of the reflective pixel electrode. The transparent pixel electrode is electrically connected to the reflective pixel electrode through the contact opening.
Abstract:
A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.
Abstract:
A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.
Abstract:
A pixel structure of a liquid crystal display (LCD) includes a scan line, a data line and a thin film transistor (TFT) disposed on the substrate. The TFT has a source electrically connected to the date line and a gate electrically connected to the scan line. A shielding electrode disposes on the substrate, wherein the same metal layer makes the shielding electrode, the source and the drain. Furthermore, the data line makes at least two different patterned metal, layers which are not formed simultaneously and the patterned metal layers are electrically connected to each other. A pixel electrode covers the part of the shielding electrode and electrically connects to the drain.
Abstract:
A pixel structure of a liquid crystal display panel and the method thereof is provided. The gate electrode and data line of the pixel structure are formed by a first patterned conductive layer, the scan line is formed by a second patterned conductive layer, and the common electrode and the pixel electrode are formed on a substrate. The common electrode, the pixel electrode, and the insulating layer disposed therebetween compose a storage capacitor. Also, the pixel or the common electrode has a slit structure.