公开(公告)号：US11049791B1

公开(公告)日：2021-06-29

申请号：US16727703

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

IPC: H01L23/373 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

公开(公告)号：US20210175192A1

公开(公告)日：2021-06-10

申请号：US16703298

申请日：2019-12-04

Applicant: Intel Corporation

Inventor： Brennen K. Mueller ,  Adel Elsherbini ,  Mauro Kobrinsky ,  Johanna Swan ,  Shawna Liff ,  Pooya Tadayon

IPC: H01L23/00

Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.

公开(公告)号：US20210098440A1

公开(公告)日：2021-04-01

申请号：US16586167

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Van Le ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Min Huang

IPC: H01L25/18 ,  G06F13/40 ,  H01L25/065 ,  H01L25/00

Abstract: Techniques and mechanisms for providing at a packaged device an integrated circuit (IC) chip and a chiplet, wherein memory resources of the chiplet are accessible by a processor core of the IC chip. In an embodiment, a hardware interface of the packaged device includes first conductive contacts at a side of the chiplet, wherein second conductive contacts of the hardware interface are electrically interconnected to the IC chip each via a respective path which is independent of the chiplet. In another embodiment, one or more of the first conductive contacts are configured to deliver power, or communicate a signal, to a device layer of one of the IC chip or the chiplet.

公开(公告)号：US20210098422A1

公开(公告)日：2021-04-01

申请号：US16586145

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

公开(公告)号：US20200043829A1

公开(公告)日：2020-02-06

申请号：US16055428

申请日：2018-08-06

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Johanna Swan

IPC: H01L23/473 ,  H01L25/065 ,  H01L23/00 ,  H01L23/522

Abstract: An integrated circuit structure may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, at least one first level channel between the substrate and the first integrated circuit device and/or at least one second level channel between the first integrated circuit device and the second integrated circuit device, and a heat dissipation device attached to the substrate which defines a fluid chamber, wherein the at least one of the first level channel and/or the at least one second level channel is opened to the fluid chamber, such that when a heat transfer fluid is introduced into the fluid chamber, the heat transfer fluid may make direct contact with the first integrated circuit device and/or the second integrated circuit device.

公开(公告)号：US20200027812A1

公开(公告)日：2020-01-23

申请号：US16040748

申请日：2018-07-20

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/498

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

公开(公告)号：US20190393193A1

公开(公告)日：2019-12-26

申请号：US16014319

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/427 ,  H01L23/10 ,  H01L23/367 ,  H01L23/498

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.

公开(公告)号：US20190393192A1

公开(公告)日：2019-12-26

申请号：US16014313

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/427 ,  H01L23/10 ,  H01L23/367 ,  H01L23/498

Abstract: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.

公开(公告)号：US20190385933A1

公开(公告)日：2019-12-19

申请号：US16007269

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/473 ,  H01L25/065 ,  H01L23/467 ,  H01L23/367 ,  H01L23/498 ,  H01L23/31

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

公开(公告)号：US20190385931A1

公开(公告)日：2019-12-19

申请号：US16007255

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/473 ,  H01L25/065 ,  H01L23/467 ,  H01L23/367 ,  H01L23/498

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.