公开(公告)号：US20240027697A1

公开(公告)日：2024-01-25

申请号：US17871558

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Wesley B. Morgan ,  Mohanraj Prabhugoud ,  David Shia ,  Eric J. M. Moret ,  Pooya Tadayon ,  Tarek A. Ibrahim

IPC: G02B6/38

CPC classification number: G02B6/3897 ,  G02B6/3885 ,  G02B6/3893

Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.

公开(公告)号：US20230197594A1

公开(公告)日：2023-06-22

申请号：US17559483

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L. Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Eric J.M. Moret ,  Pooya Tadayon

IPC: H01L23/498 ,  H05K3/32 ,  H05K1/18 ,  H01L23/538 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58

CPC classification number: H01L23/49827 ,  H05K3/32 ,  H05K1/181 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01L23/5384 ,  H01R12/58 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes a processor package including at least one processor integrated circuit (IC); an interposer including electrically conductive interposer interconnect; a first liquid metal well array including multiple liquid metal wells arranged between the processor package and the interposer, wherein the first liquid metal well array is attached to a surface of the processor package and attached to a first surface of the interposer and the interposer interconnect; a printed circuit board (PCB) attached to a second surface of the interposer and the interposer interconnect; a second liquid metal well array including a first surface attached to the first surface of the interposer and the interposer interconnect; and a first companion component package attached to a second surface of the second liquid metal well array.

公开(公告)号：US20220091511A1

公开(公告)日：2022-03-24

申请号：US17541162

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Pooya Tadayon

IPC: G03F7/20 ,  H01L27/00 ,  G03F7/30 ,  B05C3/04

Abstract: An apparatus, comprising at least one vessel having a bottom and at least one sidewall extending from the bottom, wherein the at least one sidewall encloses an interior of the at least one vessel, a shaft has a proximal end and a distal end, wherein the distal end of the shaft extends into the interior of the at least one vessel, wherein the proximal end of the shaft is coupled to a motor, at least one support structure which extends laterally from the shaft; and a substrate attachment fixture on a distal end of the at least one support structure, wherein the at least one support structure and the substrate attachment fixture are within the interior of the at least one vessel.

公开(公告)号：US11262384B2

公开(公告)日：2022-03-01

申请号：US16461387

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  David Shia

IPC: G01R1/073 ,  G01R31/28

Abstract: An embodiment includes an apparatus comprising: a substrate including a surface that comprises first, second, and third apertures; and first, second, and third probes comprising proximal ends that are respectively included within and project from the first, second, and third apertures; wherein the first, second, and third probes: (a)(i) intersect a plane that is generally coplanar with the surface, (a)(ii) include distal ends configured to contact electrical contacts of a device under test (DUT), and (a)(iii) are generally linear and each include a major axis that is non-orthogonal to the plane. Other embodiments are described herein.

公开(公告)号：US10935573B2

公开(公告)日：2021-03-02

申请号：US16145571

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  Pooya Tadayon

IPC: G01R1/06 ,  G01R1/067 ,  G01R3/00 ,  B81B7/02 ,  H01L23/00 ,  G01R31/26

Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.

公开(公告)号：US20190170810A1

公开(公告)日：2019-06-06

申请号：US15832650

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Justin Huttula

IPC: G01R31/28 ,  G01R3/00

Abstract: A testing arrangement for testing Integrated Circuit (IC) interconnects is provided. In an example, the testing arrangement includes a substrate, and a first interconnect structure. The first interconnect structure may include a first member having a first end to attach to the substrate and a second end opposite the first end, and a second member having a first end to attach to the substrate and a second end opposite the first end. In some examples, the second end of the first member and the second end of the second member are to contact a second interconnect structure of a IC device under test, and the first end of the first member and the first end of the second member are coupled such that the first member and the second member are to transmit, in parallel, current to the second interconnect structure of the IC device under test.

公开(公告)号：US12164147B2

公开(公告)日：2024-12-10

申请号：US17359178

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Pooya Tadayon ,  Zhichao Zhang ,  Liang Zhang

IPC: G02B6/122 ,  G02B6/30 ,  G02B6/42 ,  G02B6/12

Abstract: Techniques and mechanisms for optically coupling a photonic integrated circuit (PIC) chip to an optical fiber via a planar optical waveguide structure. In an embodiment, a PIC chip comprises integrated circuitry, photonic waveguides, and integrated edge-oriented couplers (IECs) which are coupled to the integrated circuitry via the photonic waveguides. The PIC chip forms respective divergent lens surfaces of the IECs, which are each at a respective terminus of a corresponding one of the photonic waveguides. A planar optical waveguide structure, which is adjacent to the IECs, comprises a core which is optically coupled between the PIC chip and an array of optical fibers. In another embodiment, an edge of the PIC forms a stepped structure, wherein an upper portion of the stepped structure comprises the plurality of coplanar IECs, and a lower portion of the stepped structure extends past the plurality of coplanar IECs.

公开(公告)号：US20240094476A1

公开(公告)日：2024-03-21

申请号：US17949417

申请日：2022-09-21

Applicant: Intel Corporation

Inventor： Wesley B. Morgan ,  David Shia ,  Mohanraj Prabhugoud ,  Eric J. M. Moret ,  Pooya Tadayon

IPC: G02B6/38

CPC classification number: G02B6/3871 ,  G02B6/3873 ,  G02B6/3887

Abstract: Technologies for pluggable optical connectors are disclosed. In the illustrative embodiment, an optical plug includes a ferrule with one or more optical fibers. The optical plug also includes a ferrule holder that holds the ferrule and a housing that encloses the ferrule and ferrule holder. The ferrule holder can move relative to the house, and the ferrule can move relative to the ferrule holder and the housing. As the optical plug is plugged into a socket, alignment features in the housing coarsely align the ferrule. Intermediate alignment features in the ferrule holder then engage, aligning the ferrule more precisely. As the optical plug is fully plugged in, fine alignment features in the ferrule engage, precisely aligning the ferrule and the optical fibers with the optical socket.

公开(公告)号：US20240027699A1

公开(公告)日：2024-01-25

申请号：US17869372

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Nicholas D. Psaila ,  Pooya Tadayon

IPC: G02B6/42

CPC classification number: G02B6/4214 ,  G02B6/4278 ,  G02B6/4244 ,  G02B6/4245 ,  G02B27/30

Abstract: Technologies for beam expansion in glass substrates are disclosed. In the illustrative embodiment, light in a waveguide defined in a glass substrate is allowed to expand towards a curved mirror defined in the glass substrate. The light is collimated to a beam as it is reflected off the mirror. In the illustrative embodiment, the light is reflected upwards toward the top surface of the glass substrate. A photonic integrated circuit (PIC) die may be mounted on the glass substrate. A micromirror lens fixed to the PIC die can focus the collimated beam into a waveguide defined in the PIC die. In some embodiments, an interface for an optical connector may be formed in the glass substrate, allowing the optical connector to be removably plugged into the glass substrate.

公开(公告)号：US11756860B2

公开(公告)日：2023-09-12

申请号：US16522443

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Shrenik Kothari ,  Chandra Mohan Jha ,  Weihua Tang ,  Robert Sankman ,  Xavier Brun ,  Pooya Tadayon

IPC: H01L23/42 ,  H01L23/522 ,  H01L23/373 ,  H01L23/367 ,  H01L25/07 ,  H01L23/538

CPC classification number: H01L23/42 ,  H01L23/367 ,  H01L23/3738 ,  H01L23/522 ,  H01L23/5384 ,  H01L25/072

Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.