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公开(公告)号:US12040307B2
公开(公告)日:2024-07-16
申请号:US16887126
申请日:2020-05-29
申请人: Intel Corporation
发明人: Feras Eid , Adel Elsherbini , Georgios Dogiamis
IPC分类号: H01L23/00
CPC分类号: H01L24/81 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/16227 , H01L2224/81222 , H01L2224/81815
摘要: Magnetic structures incorporated into integrated circuit assemblies. In some examples, the magnetic structures may enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates.
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公开(公告)号:US20240063091A1
公开(公告)日:2024-02-22
申请号:US17891735
申请日:2022-08-19
申请人: Intel Corporation
发明人: Adel Elsherbini , Feras Eid , Scot Kellar , Yoshihiro Tomita , Rajiv Mongia , Kimin Jun , Shawna Liff , Wenhao Li , Johanna Swan , Bhaskar Jyoti Krishnatreya , Debendra Mallik , Krishna Vasanth Valavala , Lei Jiang , Xavier Brun , Mohammad Enamul Kabir , Haris Khan Niazi , Jiraporn Seangatith , Thomas Sounart
IPC分类号: H01L23/473 , H01L23/00 , H01L25/065 , H01L23/367 , H01L23/373
CPC分类号: H01L23/473 , H01L24/08 , H01L25/0652 , H01L24/16 , H01L24/32 , H01L24/73 , H01L23/3677 , H01L23/3675 , H01L23/3732 , H01L23/3738 , H01L2924/3511 , H01L2224/08145 , H01L2224/08121 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/182 , H01L2924/186
摘要: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.
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公开(公告)号:US20240063072A1
公开(公告)日:2024-02-22
申请号:US17891530
申请日:2022-08-19
申请人: Intel Corporation
发明人: Adel Elsherbini , Shawna Liff , Kimin Jun , Veronica Strong , Aleksandar Aleksov , Jiraporn Seangatith , Mohammad Enamul Kabir , Johanna Swan , Tushar Talukdar , Omkar Karhade
IPC分类号: H01L23/31 , H01L25/065 , H01L23/498 , H01L21/56 , H01L23/29
CPC分类号: H01L23/3135 , H01L25/0652 , H01L25/0655 , H01L23/49816 , H01L23/49838 , H01L21/568 , H01L21/561 , H01L23/3128 , H01L23/291 , H01L24/08
摘要: Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.
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公开(公告)号:US11652059B2
公开(公告)日:2023-05-16
申请号:US17536804
申请日:2021-11-29
申请人: INTEL CORPORATION
发明人: Adel Elsherbini , Shawna Lift , Johanna Swan , Gerald Pasdast
IPC分类号: H01L23/538 , H01L21/304 , H01L21/48 , H01L23/00
CPC分类号: H01L23/5385 , H01L21/3043 , H01L21/4846 , H01L24/20
摘要: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
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公开(公告)号:US20230097714A1
公开(公告)日:2023-03-30
申请号:US17485208
申请日:2021-09-24
申请人: Intel Corporation
发明人: William J. Lambert , Beomseok Choi , Krishna Bharath , Kaladhar Radhakrishnan , Adel Elsherbini
IPC分类号: H01L23/538 , H01L25/065 , H01L23/00
摘要: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.
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公开(公告)号:US20230095608A1
公开(公告)日:2023-03-30
申请号:US17485250
申请日:2021-09-24
申请人: Intel Corporation
发明人: Adel Elsherbini , Aleksandar Aleksov , Feras Eid , Henning Braunisch , Thomas L. Sounart , Johanna Swan , Beomseok Choi , Krishna Bharath , William J. Lambert , Kaladhar Radhakrishnan
IPC分类号: H05K3/14 , H05K3/10 , H05K3/30 , H01L21/768 , H01L21/82
摘要: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.
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公开(公告)号:US20220415743A1
公开(公告)日:2022-12-29
申请号:US17358361
申请日:2021-06-25
申请人: Intel Corporation
发明人: Feras Eid , Adel Elsherbini , Johanna Swan , Shawna Liff , Aleksandar Aleksov , Julien Sebot
IPC分类号: H01L23/36 , H01L25/065 , H01L21/50 , H01L27/06 , H01L23/00
摘要: Hybrid bonded 3D die stacks with improved thermal performance, related apparatuses, systems, and methods of fabrication are disclosed. Such hybrid bonded 3D die stacks include multiple levels of dies including a level of the 3D die stack with one or more integrated circuit dies and one or more thermal dies both directly bonded to another level of the 3D die stack.
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公开(公告)号:US11476554B2
公开(公告)日:2022-10-18
申请号:US16613386
申请日:2017-07-01
申请人: Intel Corporation
发明人: Georgios Dogiamis , Sasha Oster , Telesphor Kamgaing , Erich Ewy , Adel Elsherbini , Johanna Swan
IPC分类号: H01P3/16 , H01P5/02 , B60R16/023 , H01L23/66 , H01L25/18 , H01R13/622 , H01R13/631 , H01R13/646 , H05K1/18 , H05K5/00 , H05K5/02 , H05K7/20
摘要: Embodiments of the invention include dielectric waveguides and connectors for dielectric waveguides. In an embodiment a dielectric waveguide connector may include an outer ring and one or more posts extending from the outer ring towards the center of the outer ring. In some embodiments, a first dielectric waveguide secured within the dielectric ring by the one or more posts. In another embodiment, an enclosure surrounding electronic components may include an enclosure wall having an interior surface and an exterior surface and a dielectric waveguide embedded within the enclosure wall. In an embodiment, a first end of the dielectric waveguide is substantially coplanar with the interior surface of the enclosure wall and a second end of the dielectric waveguide is substantially coplanar with the exterior surface of the enclosure wall.
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公开(公告)号:US11282812B2
公开(公告)日:2022-03-22
申请号:US16014319
申请日:2018-06-21
申请人: Intel Corporation
发明人: Adel Elsherbini , Feras Eid , Johanna Swan
IPC分类号: H01L25/065 , H01L23/373 , H01L23/498 , H01L23/10 , H01L23/367 , H01L23/427
摘要: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.
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公开(公告)号:US11270947B2
公开(公告)日:2022-03-08
申请号:US16698557
申请日:2019-11-27
申请人: Intel Corporation
发明人: Adel Elsherbini , Shawna Liff , Johanna Swan , Gerald Pasdast
IPC分类号: H01L23/538 , H01L21/304 , H01L21/48 , H01L23/00
摘要: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
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