Composite interposer structure and method of providing same

    公开(公告)号:US11652059B2

    公开(公告)日:2023-05-16

    申请号:US17536804

    申请日:2021-11-29

    申请人: INTEL CORPORATION

    摘要: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

    CONFORMAL POWER DELIVERY STRUCTURE FOR DIRECT CHIP ATTACH ARCHITECTURES

    公开(公告)号:US20230097714A1

    公开(公告)日:2023-03-30

    申请号:US17485208

    申请日:2021-09-24

    申请人: Intel Corporation

    摘要: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

    Thermal management solutions for stacked integrated circuit devices using jumping drops vapor chambers

    公开(公告)号:US11282812B2

    公开(公告)日:2022-03-22

    申请号:US16014319

    申请日:2018-06-21

    申请人: Intel Corporation

    摘要: An integrated circuit structure may be formed having a first integrated circuit device, a second integrated circuit device electrically coupled to the first integrated circuit device with a plurality of device-to-device interconnects, and at least one jumping drops vapor chamber between the first integrated circuit device and the second integrated circuit device wherein at least one device-to-device interconnect of the plurality of device-to-device interconnects extends through the jumping drops vapor chamber. In one embodiment, the integrated circuit structure may include three or more integrated circuit devices with at least two jumping drops vapor chambers disposed between the three or more integrated circuit devices. In a further embodiment, the two jumping drops chambers may be in fluid communication with one another.

    Composite interposer structure and method of providing same

    公开(公告)号:US11270947B2

    公开(公告)日:2022-03-08

    申请号:US16698557

    申请日:2019-11-27

    申请人: Intel Corporation

    摘要: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.