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101.发明授权公开(公告)号：US08756551B2
公开(公告)日：2014-06-17
申请号：US13047474
申请日：2011-03-14
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F2217/12 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/11803 , H01L2027/1182 , H01L2027/11866 , H01L2027/11874 , H01L2027/11888 , Y02P90/265
摘要： A method is provided for designing an integrated circuit device. The method includes placing four transistors of a first transistor type and four transistors of a second transistor type within a gate electrode level. Each of the transistors includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in a first direction. The transistors of the first and second transistor types are placed according to a substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction. A first linear conductive segment is placed to electrically connect the gate electrodes of the first transistors of the first and second transistor types. A second linear conductive segment is placed to electrically connect the gate electrodes of the fourth transistors of the first and second transistor types. A third linear conductive segment is placed beside either the first or second linear conductive segment.
摘要翻译： 提供了一种用于设计集成电路器件的方法。 该方法包括将第一晶体管类型的四个晶体管和第二晶体管类型的四个晶体管放置在栅极电平内。 每个晶体管包括相对于在第一方向上纵向延伸的线性形状的栅极电极段。 第一和第二晶体管类型的晶体管根据垂直于第一方向测量的基本相等的中心线对中心线间距放置。 放置第一线性导电段以电连接第一和第二晶体管类型的第一晶体管的栅电极。 放置第二线性导电段以电连接第一和第二晶体管类型的第四晶体管的栅电极。 第三线性导电段被放置在第一或第二线性导电段之外。
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102.发明申请Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level 有权集成电路与线性栅极电极中的偏移线端部间距公开(公告)号：US20130200462A1
公开(公告)日：2013-08-08
申请号：US13827615
申请日：2013-03-14
IPC分类号： H01L29/423 , G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.
摘要翻译： 第一线状导电结构（LSCS）形成第一p型晶体管和第一n型晶体管的栅电极。 第二LSCS形成第二p型晶体管的栅电极。 第三LSCS形成第二n型晶体管的栅电极，并且通过第一端对端间隔（EES）与第二LSCS分离。 第四LSCS形成第三p型晶体管的栅电极。 第五LSCS形成第三n型晶体管的栅电极，并且通过第二EES与第四LSCS分离。 第六LSCS形成第四p型晶体管和第四n型晶体管的栅电极。 与第一EES相邻的第二LSCS的端部偏离与第二EES相邻的第四LSCS的端部，和/或与第一EES相邻的第三LSCS的端部偏离第五LSCS相邻的端部 到第二个EES。
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103.发明申请Integrated Circuit Including At Least Four Linear-Shaped Conductive Structures Having Extending Portions of Different Length 有权包括具有不同长度的扩展部分的至少四个线性导电结构的集成电路公开(公告)号：US20130175639A1
公开(公告)日：2013-07-11
申请号：US13774970
申请日：2013-02-22
IPC分类号： H01L27/088 , G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes at least four linear-shaped conductive structures formed to extend lengthwise in a parallel direction to each other and each respectively including a gate electrode portion and an extending portion that extends away from the gate electrode portion. The gate electrode portions of the linear-shaped conductive structures respectively form gate electrodes of different transistors, such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of a first transistor type and does not form a gate electrode of any transistor of a second transistor type, and such that at least one of the linear-shaped conductive structures forms a gate electrode of a transistor of the second transistor type and does not form a gate electrode of any transistor of the first transistor type. Extending portions of the at least four linear-shaped conductive structures include at least two different extending portion lengths.
摘要翻译： 集成电路包括形成为沿彼此平行的方向纵向延伸的至少四个线性形状的导电结构，并且每个分别包括栅电极部分和远离栅电极部分延伸的延伸部分。 线状导电结构的栅极部分分别形成不同晶体管的栅电极，使得至少一个线状导电结构形成第一晶体管类型的晶体管的栅电极，并且不形成栅电极 并且使得至少一个线性导电结构形成第二晶体管类型的晶体管的栅电极，并且不形成第一晶体管类型的任何晶体管的栅电极。 所述至少四个线状导电结构的延伸部分包括至少两个不同的延伸部分长度。
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104.发明申请Integrated Circuit Including Gate Electrode Tracks Forming Gate Electrodes of Different Transistor Types and Linear Shaped Conductor Electrically Connecting Gate Electrodes 审中-公开包括栅极电极轨迹的集成电路形成不同晶体管类型和线形导体的栅极电极电连接栅电极公开(公告)号：US20130168777A1
公开(公告)日：2013-07-04
申请号：US13774940
申请日：2013-02-22
IPC分类号： H01L29/423
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.
摘要翻译： 集成电路包括第一栅电极轨道和第二栅电极轨道。 第一栅电极轨道包括第一栅极电极特征，其在穿过n扩散区域时形成n沟道晶体管。 第一栅极电极轨迹不与p扩散区交叉。 第二栅极电极轨道包括第二栅极电极特征，其在与p扩散区域交叉时形成p沟道晶体管。 第二栅电极轨迹不与n扩散区交叉。 集成电路还包括在垂直于第一和第二栅极电极轨迹的参考方向上与第一和第二栅电极特征相交的直线形导体。 线状导体提供第一和第二栅电极特征之间的电连接。
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105.发明授权Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restriction 有权具有栅极电平的半导体器件包括第一类型的晶体管和具有相应的栅极接触放置限制的第二型晶体管公开(公告)号：US08258551B2
公开(公告)日：2012-09-04
申请号：US12572228
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 半导体器件的单元包括扩散级，包括由非活性区分隔的多个扩散区。 电池还包括栅电极级，其包括限定为仅在第一平行方向上延伸的导电特征。 通过各自的起始布局特征制造相邻的导电特征，其在第一平行方向上共享公共线的范围，该特征通过端对端间隔而彼此分开，该端对端间隔的栅极电极的尺寸基本相等 并且被最小化到半导体器件制造能力允许的程度。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 多个PMOS晶体管器件等于电池中的NMOS晶体管器件的数量。 电池还包括形成在栅极电极上方的多个互连电平。
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106.发明授权Methods for defining and utilizing sub-resolution features in linear topology 有权在线性拓扑中定义和利用子分辨率特征的方法公开(公告)号：US08225239B2
公开(公告)日：2012-07-17
申请号：US12479674
申请日：2009-06-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： Regular layout shapes are placed in accordance with a virtual grate. A determination is made as to whether an unoccupied layout space adjacent to a regular layout shape to be reinforced, and extending in a direction perpendicular to the regular layout shape, is large enough to support placement of a sub-resolution shape. Upon determining that the unoccupied layout space is large enough to support placement of the sub-resolution shape, the sub-resolution shape is placed so as to be substantially centered upon a virtual line of the virtual grate within the unoccupied layout space. Also, one or more sub-resolution shapes are placed between and parallel with neighboring regular layout shapes when windows of lithographic reinforcement associated with each of the neighboring regular layout shapes permit. The sub-resolution shapes may be placed according to a virtual grate, or may be placed based on proximity to edges of the neighboring regular layout shapes.
摘要翻译： 正常的布局形状根据虚拟炉排放置。 确定与正规布局形状相邻的未被占用的布局空间是否被加强并且沿与正常布局形状垂直的方向延伸的尺寸足够大以支持分分辨率形状的放置。 在确定未占用的布局空间足够大以支持分分辨率形状的放置时，子分辨率形状被放置为基本上位于未占用的布局空间内的虚拟格栅的虚拟线上。 此外，当与相邻的规则布局形状中的每一个相关联的光刻加固件的窗口允许时，一个或多个子分辨率形状被放置在相邻的规则布局形状之间并与其平行。 子分辨率形状可以根据虚拟格栅放置，或者可以基于邻近的规则布局形状的边缘的位置放置。
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107.发明授权Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structures 有权集成电路包括至少六个线形导电结构，形成具有超过导电接触结构的至少两个不同延伸距离的晶体管的栅电极公开(公告)号：US08129756B2
公开(公告)日：2012-03-06
申请号：US12572221
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device is disclosed to include a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level includes conductive features defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features is less than a wavelength of light used in a photolithography process for their fabrication.
摘要翻译： 公开了一种半导体器件的电池，其包括扩散级，其包括由非活性区域分开的多个扩散区域。 电池还包括栅极电极级，其包括限定为仅在第一平行方向上延伸的导电特征。 通过各自的起始布局特征制造相邻的导电特征，其在第一平行方向上共享公共线的范围，该特征通过端对端间隔而彼此分开，该端对端间隔的栅极电极的尺寸基本相等 并且被最小化到半导体器件制造能力允许的程度。 栅极电极级包括沿着沿着第一平行方向的至少四个不同的虚拟线限定的导电特征。 导电特征的宽度小于用于其制造的光刻工艺中使用的光的波长。
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108.发明授权Integrated circuit including gate electrode level region including at least seven linear-shaped conductive structures of equal length positioned at equal pitch with at least two linear-shaped conductive structures each forming one transistor and having extending portion sized greater than gate portion 有权集成电路，包括栅电极电平区域，包括至少七个相等长度的直线形导电结构，其等同距离与至少两个线形导电结构形成，每个形成一个晶体管，并具有尺寸大于栅极部分的延伸部分公开(公告)号：US08129753B2
公开(公告)日：2012-03-06
申请号：US12567648
申请日：2009-09-25
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions. The layout of the cell also includes a gate electrode level layout defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.
摘要翻译： 公开了半导体器件的单元的布局，以包括扩散级布局，其包括多个扩散区布局形状，包括p型扩散区域和n型扩散区域。 电池的布局还包括限定为包括多个线性形状布局特征的栅电极层布局，其布置为仅在第一平行方向上延伸。 限制布局区域的栅极电平布局中的线形布局特征中的每一个都是矩形的。 栅极电平布局内的线形布局特征在p型和/或n型扩散区中的一个或多个上延伸以形成PMOS和NMOS晶体管器件。 单元中的PMOS和NMOS晶体管器件的总数大于或等于8。
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109.发明授权公开(公告)号：US08129752B2
公开(公告)日：2012-03-06
申请号：US12567565
申请日：2009-09-25
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion including a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual bisecting line. A gate electrode level region above the substrate portion includes a number of conductive features that extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features separated by an equal and minimal sized end-to-end spacing. Conductive features are defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within a photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. The photolithographic interaction radius is five times the wavelength of light used in the photolithography process.
摘要翻译： 半导体器件包括：衬底部分，其包括相对于虚拟平分线以非对称方式限定的多个扩散区域。 基板部分上方的栅极电极区域包括仅沿第一平行方向延伸的多个导电特征。 在相同的起始布局特征上由相同且最小尺寸的端对端间隔分开的相邻导电特征共享在第一并行方向上的公共线。 导电特征沿着沿着第一并行方向的至少四个不同的虚拟线程限定。 在光刻相互作用半径内的导电特征的宽度小于在其制造的光刻工艺中使用的193纳米的光的波长。 光刻相互作用半径是光刻工艺中使用的光的波长的五倍。
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110.发明授权Integrated circuit device with linearly defined gate electrode level region and shared diffusion region of first type connected to shared diffusion region of second type through at least two interconnect levels 有权具有线性限定的栅极电平区域和第一类型的共享扩散区域的集成电路装置通过至少两个互连级别连接到第二类型的共享扩散区域公开(公告)号：US08110854B2
公开(公告)日：2012-02-07
申请号：US12567574
申请日：2009-09-25
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
摘要翻译： 半导体器件包括其中限定有多个扩散区的衬底部分。 该半导体器件包括包含多个导电特征的栅极电平区域，该导电特征被限定为只在第一平行方向上延伸。 在第一并行方向上共享公共线路的相同数量的导电特征的相邻的导电特征由相应的起始布局特征制成，所述相互起始布局特征通过端对端间隔彼此分开，所述端对端间隔具有在 栅极电极水平区域并且被最小化到半导体器件制造能力允许的程度。 栅极电极区域内的一些导电特征在多个扩散区域上延伸以形成PMOS或NMOS晶体管器件。 多个PMOS晶体管器件等于栅电极电平区域中的NMOS晶体管器件的数量。
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