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公开(公告)号：US20230411396A1
公开(公告)日：2023-12-21
申请号：US18461371
申请日：2023-09-05
申请人： SOCIONEXT INC.
发明人： Toshio HINO , Junji IWAHORI
IPC分类号： H01L27/118 , H01L21/8238 , H01L29/78 , H01L27/06 , H01L27/02
CPC分类号： H01L27/11807 , H01L21/823871 , H01L21/823821 , H01L29/78 , H01L27/0629 , H01L27/0207 , H01L2027/11812 , H01L2027/11862 , H01L2027/11866 , H01L2027/11881 , H01L2027/11892
摘要： The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.
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公开(公告)号：US11764224B2
公开(公告)日：2023-09-19
申请号：US17887913
申请日：2022-08-15
申请人： SOCIONEXT INC.
发明人： Hiroyuki Shimbo
IPC分类号： H01L27/00 , H01L27/118 , H01L29/06 , H01L27/092 , H01L27/02 , H01L21/8238
CPC分类号： H01L27/11807 , H01L27/0207 , H01L27/092 , H01L29/06 , H01L21/823871 , H01L2027/11812 , H01L2027/11861 , H01L2027/11864 , H01L2027/11866
摘要： Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.
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公开(公告)号：US09905576B2
公开(公告)日：2018-02-27
申请号：US15696728
申请日：2017-09-06
IPC分类号： H01L27/118 , H01L29/423 , H01L23/522 , H01L21/8238 , H01L27/088 , H01L27/02 , H01L27/092 , G06F17/50 , H01L21/28 , H01L23/528
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.
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公开(公告)号：US20170358600A1
公开(公告)日：2017-12-14
申请号：US15688187
申请日：2017-08-28
IPC分类号： H01L27/118 , H01L23/528 , H01L27/088 , H01L27/092 , H01L27/02 , H01L29/423 , H01L21/8238 , H01L21/28 , G06F17/50 , H01L23/522
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.
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公开(公告)号：US20170069659A1
公开(公告)日：2017-03-09
申请号：US15063115
申请日：2016-03-07
发明人： Atsushi KAWASUMI
IPC分类号： H01L27/118
CPC分类号： H01L27/11807 , H01L27/1104 , H01L27/11582 , H01L28/00 , H01L2027/11812 , H01L2027/11838 , H01L2027/11848 , H01L2027/11864 , H01L2027/11881
摘要： According to one embodiment, a semiconductor memory 100 includes a memory cell array 100A composed of a plurality of SRAM cells 10 including NMOS transistors and PMOS transistors, and a bias circuit 100B connected to a ground GND1 or power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes NMOS transistors 121, 122, 133 and 134 that are same as the NMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion, and PMOS transistors 111 and 112 that are same as the PMOS transistors of the SRAM cells 10 in terms of channel length and channel width and in terms of dopant and dose amount at a channel portion. Diffusion regions of the NMOS transistors and the PMOS transistors are formed in a same semiconductor layer.
摘要翻译： 根据一个实施例，半导体存储器100包括由包括NMOS晶体管和PMOS晶体管的多个SRAM单元10组成的存储单元阵列100A，以及连接到存储单元阵列的接地GND1或电源电压VDD1的偏置电路100B 100A。 偏置电路100B包括在沟道长度和沟道宽度以及沟道部分的掺杂剂和剂量方面与SRAM单元10的NMOS晶体管相同的NMOS晶体管121,122,133和134以及PMOS晶体管 111和112在沟道长度和沟道宽度方面与SRAM单元10的PMOS晶体管相同，并且就沟道部分的掺杂剂和剂量而言是相同的。 NMOS晶体管和PMOS晶体管的扩散区域形成在相同的半导体层中。
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6.发明授权Integrated circuit including linear gate electrode structures having different extension distances beyond contact 有权集成电路包括具有不同延伸距离超过接触的线性栅电极结构公开(公告)号：US08921896B2
公开(公告)日：2014-12-30
申请号：US13827755
申请日：2013-03-14
IPC分类号： H01L27/10 , H01L27/02 , H01L27/092
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A first linear-shaped conductive structure (LSCS) forming gate electrodes of both a first p-transistor and a first n-transistor. A second LSCS forming a gate electrode of a second p-transistor and including an extension portion extending away therefrom. A third LSCS forming a gate electrode of a second n-transistor and including an extension portion extending away therefrom. A fourth LSCS forming a gate electrode of a third p-transistor and including an extension portion extending away therefrom. A fifth LSCS forming a gate electrode of a third n-transistor and including an extension portion extending away therefrom. A sixth LSCS forming gate electrodes of both a fourth p-transistor and a fourth n-transistor. Four contact structures respectively contacting the extension portions of the second, third, fourth, and fifth LSCS's, such that at least two of the extension portions extend different distances beyond their contact structure.
摘要翻译： 形成第一p型晶体管和第一n型晶体管的栅电极的第一线性形状导电结构（LSCS）。 形成第二p晶体管的栅电极并且包括从其延伸的延伸部分的第二LSCS。 第三LSCS形成第二n型晶体管的栅电极，并且包括从其延伸的延伸部分。 形成第三p晶体管的栅电极并且包括从其延伸的延伸部分的第四LSCS。 形成第三n型晶体管的栅电极并且包括从其延伸的延伸部分的第五LSCS。 形成第四p型晶体管和第四n型晶体管的栅电极的第六LSCS。 四个接触结构分别接触第二，第三，第四和第五LSCS的延伸部分，使得至少两个延伸部分延伸超过其接触结构的不同距离。
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7.发明授权Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset ends 有权半导体器件包括至少六个形成具有至少两个晶体管的晶体管形成线形的晶体管，其形成具有偏移端的线公开(公告)号：US08258552B2
公开(公告)日：2012-09-04
申请号：US12572243
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.
摘要翻译： 半导体器件的单元包括扩散级，包括由非活性区分隔的多个扩散区。 电池包括栅极电极级，其包括限定为仅在第一平行方向上延伸的导电特征。 在相同的起始布局特征中，通过端对端间隔彼此分离的相应的导电特征，其在第一平行方向上共享共同的范围的相邻导电特征，其尺寸基本相等并且跨越栅极电极级最小化 地区。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 单元中的PMOS和NMOS晶体管器件的总数大于或等于8。 在五波长光刻相互作用半径内的导电特征的宽度小于用于其制造的光刻工艺中使用的193纳米的光的波长。
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8.发明授权Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion length 有权集成电路包括至少三个线性形状的导电结构，其等间距包括具有大于栅极部分长度的非栅极部分长度的线形导电结构公开(公告)号：US08134186B2
公开(公告)日：2012-03-13
申请号：US12572237
申请日：2009-10-01
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.
摘要翻译： 半导体器件的单元包括扩散级，包括由非活性区分隔的多个扩散区。 电池还包括栅极电极级，其包括限定为仅在第一平行方向上延伸的导电特征。 通过各自的起始布局特征制造相邻的导电特征，其在第一平行方向上共享公共线的范围，该特征通过端对端间隔而彼此分开，该端对端间隔的栅极电极的尺寸基本相等 并且被最小化到半导体器件制造能力允许的程度。 一些导电特征形成相应的PMOS和/或NMOS晶体管器件。 单元中的PMOS和NMOS晶体管器件的总数大于或等于8。 电池还包括形成在栅极电极上方的多个互连电平。
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9.发明授权Integrated circuit device with gate level region including non-gate linear conductive segment positioned within 965 nanometers of four transistors of first type and four transistors of second type 有权具有栅极电平区域的集成电路装置，包括位于第一类型的四个晶体管的965纳米内的非栅极线性导电段和第二类型的四个晶体管公开(公告)号：US08101975B2
公开(公告)日：2012-01-24
申请号：US12567602
申请日：2009-09-25
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The semiconductor device includes a gate electrode level region including a number of conductive features defined to extend in only a first parallel direction. Adjacent ones of the number of conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features within the gate electrode level region extend over the plurality of diffusion regions to form PMOS or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the gate electrode level region is greater than or equal to eight.
摘要翻译： 半导体器件包括其中限定有多个扩散区的衬底部分。 该半导体器件包括包含多个导电特征的栅极电平区域，该导电特征被限定为只在第一平行方向上延伸。 在第一并行方向上共享公共线路的相同数量的导电特征的相邻的导电特征由相应的起始布局特征制成，所述各个起始布局特征通过端对端间隔彼此分离，所述端对端间隔具有在 栅极电极水平区域并且被最小化到半导体器件制造能力允许的程度。 栅极电极区域内的一些导电特征在多个扩散区域上延伸以形成PMOS或NMOS晶体管器件。 栅极电极区域中的PMOS和NMOS晶体管器件的总数大于或等于8。
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10.发明申请Semiconductor Device Portion Having Sub-193 Nanometers -Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions 有权具有Sub-193纳米级的半导体器件部分 - 由直线形栅极电极形成的栅极导电结构布局特征定义为具有最小端对端间隔和具有相应的非对称扩散区域的至少四个栅极电极轨迹公开(公告)号：US20100032726A1
公开(公告)日：2010-02-11
申请号：US12567565
申请日：2009-09-25
IPC分类号： H01L27/04
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion including a plurality of diffusion regions defined in a non-symmetrical manner relative to a virtual bisecting line. A gate electrode level region above the substrate portion includes a number of conductive features that extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features separated by an equal and minimal sized end-to-end spacing. Conductive features are defined along at least four different virtual lines of extent in the first parallel direction. A width of the conductive features within a photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication. The photolithographic interaction radius is five times the wavelength of light used in the photolithography process.
摘要翻译： 半导体器件包括：衬底部分，其包括相对于虚拟平分线以非对称方式限定的多个扩散区域。 基板部分上方的栅极电极区域包括仅沿第一平行方向延伸的多个导电特征。 在相同的起始布局特征上由相同且最小尺寸的端对端间隔分开的相邻导电特征共享第一并行方向上的公共线。 导电特征沿着沿着第一并行方向的至少四个不同的虚拟线程限定。 在光刻相互作用半径内的导电特征的宽度小于在其制造的光刻工艺中使用的193纳米的光的波长。 光刻相互作用半径是光刻工艺中使用的光的波长的五倍。
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