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公开(公告)号：US12160600B2
公开(公告)日：2024-12-03
申请号：US18331800
申请日：2023-06-08
Inventor： Chong Soon Lim , Sughosh Pavan Shashidhar , Ru Ling Liao , Hai Wei Sun , Han Boon Teo , Jing Ya Li , Kiyofumi Abe , Tadamasa Toma , Takahiro Nishi
IPC: H04N19/44 , H04N19/119 , H04N19/137 , H04N19/159 , H04N19/176
Abstract: An image decoder has circuitry coupled to a memory. The circuitry splits a current image block into a plurality of partitions. The circuitry predicts a first motion vector from a set of uni-prediction motion vector candidates for a first partition of the plurality of partitions, and decodes the first partition using the first motion vector.
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102.发明授权公开(公告)号：US12149745B2
公开(公告)日：2024-11-19
申请号：US17834194
申请日：2022-06-07
Inventor： Takahiro Nishi , Tadamasa Toma , Kiyofumi Abe , Yusuke Kato
IPC: H04N19/70 , H04N19/105 , H04N19/154 , H04N19/169 , H04N19/172 , H04N19/29 , H04N19/30
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, for a group of layers including at least one output layer, the circuitry generates a bitstream including a common header for one or more layers in the group of layers, in which when a total number of layers in the group of layers is 1, (i) performance requirement information indicating a performance requirement for a decoder is signaled in the common header, and (ii) a hypothetical reference decoder (HRD) parameter is not signaled in the common header. The bitstream includes the common header and encoded data of at least one image in the at least one output layer. The common header does not include the HRD parameter.
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公开(公告)号：US12149686B2
公开(公告)日：2024-11-19
申请号：US18296272
申请日：2023-04-05
Inventor： Ryuichi Kanoh , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/117 , H04N19/14 , H04N19/159 , H04N19/174
Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. The processing circuitry is configured to: select a filter based at least on a prediction mode used for a first block, the filter including first filter coefficients for the first block and second filter coefficients for a second block; multiply values of first pixels among the first block and second pixels among the second block by the first filter coefficients to change a value of a first pixel in the first pixels; and multiply the values of the first pixels among the first block and the second pixels among the second block by the second filter coefficients to change a value of a second pixel in the second pixels.
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公开(公告)号：US20240380921A1
公开(公告)日：2024-11-14
申请号：US18779814
申请日：2024-07-22
Inventor： Kiyofumi ABE , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/52 , H04N19/137 , H04N19/176 , H04N19/186
Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.
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公开(公告)号：US12143583B2
公开(公告)日：2024-11-12
申请号：US17071470
申请日：2020-10-15
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/12 , H04N19/126 , H04N19/159 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry: performs a transform process of (i) applying a first transform to a prediction residual signal indicating a difference between a current block to be encoded and a prediction image of the current block and (ii) further applying a second transform to a transform result of the first transform; and in the second transform, selects one transform basis (i) from a first group of candidates when a size of the current block is a first block size and (ii) from a second group of candidates when the size of the current block is a second block size different from the first block size, the first group including one or more candidates for a transform basis, the second group being different from the first group.
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Patent Agency Ranking
公开(公告)号：US12137236B2
公开(公告)日：2024-11-05
申请号：US18235960
申请日：2023-08-21
Inventor： Virginie Drugeon , Tadamasa Toma , Takahiro Nishi , Kiyofumi Abe , Ryuichi Kanoh
IPC: H04N19/189 , H04N19/105 , H04N19/132 , H04N19/159 , H04N19/182
Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: derives a one-dimensional array of a plurality of reference samples for intra prediction; performs smoothing on the one-dimensional array of the plurality of reference samples which has been derived; and generates a prediction image using the plurality of reference samples. In deriving the one-dimensional array, the circuitry projects a value of at least one decoded pixel located on a first line onto a second line perpendicular to the first line, to derive at least one of the plurality of reference samples, and the smoothing is performed on the at least one decoded pixel projected onto the second line.
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公开(公告)号：US20240333934A1
公开(公告)日：2024-10-03
申请号：US18738296
申请日：2024-06-10
Inventor： Kiyofumi ABE , Takahiro Nishi , Tadamasa Toma , Yusuke Kato
IPC: H04N19/13 , H04L65/70 , H04L65/75 , H04N19/176 , H04N19/184 , H04N19/70
CPC classification number: H04N19/13 , H04L65/70 , H04L65/75 , H04N19/176 , H04N19/184 , H04N19/70
Abstract: An encoder includes memory and circuitry which: (i) encodes an image block; (ii) when encoding the image block: binarizes coefficient information indicating coefficients of the image block; and controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and (iii) when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is applied to the data string and a predetermined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is applied to the data string and the predetermined condition is satisfied; binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is applied to the data string; and subtracts 1 from a value of an initial non-zero coefficient when no arithmetic encoding is applied to the data string when encoding the image block.
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公开(公告)号：US12108073B2
公开(公告)日：2024-10-01
申请号：US18217840
申请日：2023-07-03
Inventor： Jing Ya Li , Chong Soon Lim , Ru Ling Liao , Han Boon Teo , Hai Wei Sun , Che Wei Kuo , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/00 , H04N19/139 , H04N19/159 , H04N19/176 , H04N19/513
CPC classification number: H04N19/513 , H04N19/139 , H04N19/159 , H04N19/176
Abstract: Provided is an encoder including circuitry and memory coupled to the circuitry. A prediction mode for a current block is an affine mode, and in operation, the circuitry: derives a base motion vector which is a motion vector to be used in a prediction process for the current block, and is a motion vector at an affine-mode control point in the current block; derives a first motion vector different from the base motion vector; derives a motion vector difference based on a difference between the base motion vector and the first motion vector; determines whether the motion vector difference is greater than a threshold; if so, modifies a second motion vector different from the base motion vector and the first motion vector, and if not, does not modify the second motion vector; and encodes the current block using the second motion vector modified or the second motion vector not modified.
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109.发明授权公开(公告)号：US12101496B2
公开(公告)日：2024-09-24
申请号：US17517066
申请日：2021-11-02
Inventor： Virginie Drugeon , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Yusuke Kato
IPC: H04N19/44 , H04N19/159 , H04N19/172 , H04N19/46
CPC classification number: H04N19/44 , H04N19/159 , H04N19/172 , H04N19/46
Abstract: Circuitry of a decoder is configured to decode an image according to a coding structure including an intra random access point (IRAP) picture, leading pictures to be output before the IRAP picture in output order, and trailing pictures to be output after the IRAP picture in the output order. When the image is decoded, the circuitry decodes, according to a flag in a bitstream, at most one trailing picture among the trailing pictures before decoding the leading pictures in decoding order, and decodes the trailing pictures other than the at most one trailing picture after decoding the leading pictures in the decoding order. The flag indicates whether a picture of each of access units in the bitstream is a field picture. The circuitry decodes the at most one trailing picture before decoding the leading pictures in the decoding order when the flag indicates that the picture is a field picture.
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公开(公告)号：US12088849B2
公开(公告)日：2024-09-10
申请号：US17832973
申请日：2022-06-06
Inventor： Virginie Drugeon , Tadamasa Toma , Takahiro Nishi , Kiyofumi Abe , Yusuke Kato
IPC: H04N19/00 , H04N19/132 , H04N19/167 , H04N19/186 , H04N19/70
CPC classification number: H04N19/70 , H04N19/132 , H04N19/167 , H04N19/186
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry determines whether or not a current video to be processed is a progressive video. When it is determined that the current video is a progressive video, the encoder encodes, into a bitstream, one syntax element indicating a chroma location type which is information indicating locations of chroma samples relative to luma samples for a frame included in the current video. When it is determined that the current video is not a progressive video, the encoder encodes two syntax elements into the bitstream, each of which indicates the chroma location type for a different one of fields of two types included in the current video.
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