公开(公告)号：US12206882B2

公开(公告)日：2025-01-21

申请号：US18510430

申请日：2023-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Ru Ling Liao ,  Han Boon Teo ,  Takahiro Nishi ,  Ryuichi Kanoh ,  Tadamasa Toma

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/124 ,  H04N19/13 ,  H04N19/159 ,  H04N19/176 ,  H04N19/96

Abstract: An image encoder writes a first parameter and a second parameter to a bitstream, and derives a partition mode based on the first and second parameters. Responsive to the derived partition mode being a first partition mode, the image encoder executes the first partition mode including: splitting a block of a picture into a plurality of first blocks including a N×2N block sized N pixels by 2N pixels; splitting the N×2N block, wherein a ternary split is allowed to split the N×2N block in a vertical direction, which is a direction along the 2N pixels, into a plurality of sub blocks including at least one sub block sized N/4×2N, while a binary split is not allowed to split the N×2N block in the vertical direction into two sub blocks that are equally sized N/2×2N; and encoding the plurality of sub blocks.

公开(公告)号：US12184852B2

公开(公告)日：2024-12-31

申请号：US18530032

申请日：2023-12-05

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Sughosh Pavan Shashidhar ,  Hai Wei Sun ,  Chong Soon Lim ,  Ru Ling Liao ,  Han Boon Teo ,  Jing Ya Li ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh ,  Tadamasa Toma

IPC: H04N11/02 ,  H04N19/119 ,  H04N19/176 ,  H04N19/184 ,  H04N19/60

Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; and encodes the plurality of sub blocks. The minimum threshold value corresponds to a minimum size supported in a transform process.

公开(公告)号：US12167007B2

公开(公告)日：2024-12-10

申请号：US17675444

申请日：2022-02-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Che-Wei Kuo ,  Hai Wei Sun ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/423 ,  H04N19/172 ,  H04N19/174 ,  H04N19/70

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry encodes second information indicating whether first information is present in a bitstream, the first information being regarding a subpicture which is a rectangular region in a picture, the picture including slices, and when the second information indicates that the first information is present in the bitstream, each of the slices is a rectangular slice and has a subpicture index indicating a subpicture to which the slice belongs.

公开(公告)号：US20240364916A1

公开(公告)日：2024-10-31

申请号：US18768349

申请日：2024-07-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/513 ,  H04N19/132 ,  H04N19/176 ,  H04N19/563

CPC classification number: H04N19/513 ,  H04N19/132 ,  H04N19/176 ,  H04N19/563

Abstract: The present disclosure provides systems and methods for video coding. The systems include, for example, an image encoder comprising: circuitry; and a memory coupled to the circuitry, wherein the circuitry, in operation, performs the following: predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture; padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block; calculating at least a gradient using the second block of prediction samples; and encoding the current block using at least the calculated gradient.

公开(公告)号：US12126795B2

公开(公告)日：2024-10-22

申请号：US17943971

申请日：2022-09-13

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling Liao ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Sughosh Pavan Shashidhar ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.

公开(公告)号：US12088791B2

公开(公告)日：2024-09-10

申请号：US17946784

申请日：2022-09-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling Liao ,  Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Sughosh Pavan Shashidhar ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

CPC classification number: H04N19/105 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46

Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.

公开(公告)号：US20240297986A1

公开(公告)日：2024-09-05

申请号：US18657222

申请日：2024-05-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Yusuke Kato ,  Tadamasa Toma ,  Kiyofumi Abe ,  Takahiro Nishi

IPC: H04N19/107 ,  H04N19/176

CPC classification number: H04N19/107 ,  H04N19/176

Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.

公开(公告)号：US12081748B2

公开(公告)日：2024-09-03

申请号：US17868199

申请日：2022-07-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Han Boon Teo ,  Hai Wei Sun ,  Chong Soon Lim ,  Jing Ya Li ,  Chu Tong Wang ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/117 ,  H04N19/105 ,  H04N19/46 ,  H04N19/80

CPC classification number: H04N19/117 ,  H04N19/105 ,  H04N19/46 ,  H04N19/80

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry: executes a second process of applying a second filter to the first image to generate a second image, not holding the second image as a reference image, holding the first image as a reference image, and displaying the second image; writes coefficients of each of one or more filter candidates that are candidates for the second filter into a bitstream, wherein the coefficients are included in a first storage location when written into the bitstream; and writes a parameter that specifies, for each image, one of the one or more filter candidates as the second filter into the bitstream, wherein the parameter is included in a second storage location when written into the bitstream, and the second storage location is different from the first storage location.

公开(公告)号：US12063390B2

公开(公告)日：2024-08-13

申请号：US18242747

申请日：2023-09-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Han Boon Teo ,  Takahiro Nishi ,  Tadamasa Toma ,  Ru Ling Liao ,  Sughosh Pavan Shashidhar ,  Hai Wei Sun

IPC: H04N19/597 ,  G06T5/80 ,  H04N5/00 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46 ,  H04N19/85

CPC classification number: H04N19/597 ,  G06T5/80 ,  H04N19/159 ,  H04N19/176 ,  H04N19/46 ,  H04N19/85

Abstract: An encoder capable of properly handling an image to be encoded or decoded includes processing circuitry and memory connected to the processing circuitry. Using the memory, the processing circuitry: obtains parameters including at least one of (i) one or more parameters related to a first process for correcting distortion in an image captured with a wide angle lens and (ii) one or more parameters related to a second process for stitching a plurality of images; generates an encoded image by encoding a current image to be processed that is based on the image or the plurality of images; and writes the parameters into a bitstream including the encoded image.

公开(公告)号：US12063383B2

公开(公告)日：2024-08-13

申请号：US18103567

申请日：2023-01-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/513 ,  H04N19/132 ,  H04N19/176 ,  H04N19/563

CPC classification number: H04N19/513 ,  H04N19/132 ,  H04N19/176 ,  H04N19/563

Abstract: The present disclosure provides systems and methods for video coding. The systems include, for example, an image encoder comprising: circuitry; and a memory coupled to the circuitry, wherein the circuitry, in operation, performs the following: predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture; padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block; calculating at least a gradient using the second block of prediction samples; and encoding the current block using at least the calculated gradient.