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101.发明申请公开(公告)号：US20210104009A1
公开(公告)日：2021-04-08
申请号：US16591528
申请日：2019-10-02
Applicant: QUALCOMM Incorporated
Inventor： Liang Li , Andrew Evan Gruber
Abstract: Methods, systems, and devices for image processing are described. A device may identify a target pixel having a texel coordinate in an image. The device may select, based on the texel coordinate, a first texel sample of a first set of texel samples and a second texel sample of a second set of texel samples. In some examples, the device may group the first texel sample and the second texel sample into a third set of texel samples. The device may generate an instruction including the third set of texel samples and a weighted sum associated with the first texel sample and the second texel sample, and process the third set of texel samples based on the instruction. In some examples, the instruction may be a macro instruction.
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公开(公告)号：US10521321B2
公开(公告)日：2019-12-31
申请号：US15850967
申请日：2017-12-21
Applicant: QUALCOMM Incorporated
Inventor： Alex Kwang Ho Jong , Jay Chunsup Yun , Donghyun Kim , Rahul Gulati , Brendon Lewis Johnson , Andrew Evan Gruber
IPC: G06F11/00 , G06F11/277 , G06T1/20 , G06T7/00 , G06F11/22
Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.
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公开(公告)号：US10467723B2
公开(公告)日：2019-11-05
申请号：US15850907
申请日：2017-12-21
Applicant: QUALCOMM Incorporated
Inventor： Brendon Lewis Johnson , Andrew Evan Gruber , Jay Chunsup Yun , Rahul Gulati , Donghyun Kim , Alex Kwang Ho Jong
Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.
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公开(公告)号：US10430912B2
公开(公告)日：2019-10-01
申请号：US15432170
申请日：2017-02-14
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Lin Chen
Abstract: A GPU may be configured to detect and nullify unnecessary instructions. Nullifying unnecessary instructions include overwriting a detected unnecessary instruction with a no operation (NOP) instruction. In another example, nullifying unnecessary instructions may include writing a value to a 1-bit instruction memory. Each bit of the 1-bit instruction memory may be associated with a particular instruction of the draw call. If the 1-bit instruction memory has a true value (e.g., 1), the GPU is configured to not execute the particular instruction.
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公开(公告)号：US20190087930A1
公开(公告)日：2019-03-21
申请号：US15707608
申请日：2017-09-18
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber
Abstract: A method for memory bandwidth compression comprising analyzing a texture surface to identify one or more areas of the texture surface that are fetchable with lower memory bandwidth consumption as compared to other areas of the texture surface, adding metadata to a metadata surface associated with the texture surface based on the analysis, the metadata indicating the one or more areas of the texture surface that are fetchable with lower memory bandwidth consumption as compared to other areas of the texture surface, and fetching the texture surface in accordance with the metadata.
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Patent Agency Ranking
公开(公告)号：US10157443B1
公开(公告)日：2018-12-18
申请号：US15662933
申请日：2017-07-28
Applicant: QUALCOMM Incorporated
Abstract: The techniques of this disclosure include deferred batching of incremental constant loads. Graphics APIs include the ability to use lightweight constants for use by shaders. A buffer is allocated by a graphics processing unit (GPU) driver that contains a snapshot of the current lightweight constants. This may provide a complete set of state to serve as a starting point. From then on updates to the lightweight constants may be appended to this buffer in an incremental fashion by inserting the update and increasing the size of the buffer by a command processor on a graphics processing unit (GPU). The incremental nature of the updates may be captured, but removes the need for issuing them on every draw call and instead the incremental updates may be batch processed when a live draw call is encountered.
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公开(公告)号：US10115175B2
公开(公告)日：2018-10-30
申请号：US15048599
申请日：2016-02-19
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Pramod Vasant Argade , Jing Wu
Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.
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公开(公告)号：US20170243320A1
公开(公告)日：2017-08-24
申请号：US15048599
申请日：2016-02-19
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Pramod Vasant Argade , Jing Wu
CPC classification number: G06T1/20 , G06F9/30072 , G06F9/3851 , G06F9/3887 , G06T5/008
Abstract: A method for processing data in a graphics processing unit including receiving an indication that all threads of a warp in a graphics processing unit (GPU) are to execute a same branch in a first set of instructions, storing one or more predicate bits in a memory as a single set of predicate bits, wherein the single set of predicate bits applies to all of the threads in the warp, and executing a portion of the first set of instructions in accordance with the single set of predicate bits. Executing the first set of instructions may include executing the first set of instruction in accordance with the single set of predicate bits using a single instruction, multiple data (SIMD) processing core and/or executing the first set of instruction in accordance with the single set of predicate bits using a scalar processing unit.
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公开(公告)号：US09645792B2
公开(公告)日：2017-05-09
申请号：US14461890
申请日：2014-08-18
Applicant: QUALCOMM Incorporated
Inventor： Pramod Vasant Argade , Andrew Evan Gruber , Chiente Ho , Stewart Griffin Hall , Lin Chen
CPC classification number: G06F7/5443 , G06F5/01 , G06F7/483 , G06F7/57
Abstract: At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.
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公开(公告)号：US09569811B2
公开(公告)日：2017-02-14
申请号：US14316275
申请日：2014-06-26
Applicant: QUALCOMM Incorporated
Inventor： Andrew Evan Gruber , Tao Wang , Chunhui Mei , Gang Zhong , Feng Ge
CPC classification number: G06T1/20 , G06T11/40 , G06T15/005 , G09G5/363 , G09G2340/0407 , G09G2360/122
Abstract: In an example, a method for rendering graphics data includes rendering pixels of a first bin of a plurality of bins, wherein the pixels of the first bin are associated with a first portion of an image, and rendering, to the first bin, one or more pixels that are located outside the first portion of the image and associated with a second, different bin of the plurality of bins. The method also includes rendering the one or more pixels associated with the second bin to the second bin, such that the one or more pixels are rendered to both the first bin and the second bin.
Abstract translation: 在一个示例中，用于渲染图形数据的方法包括渲染多个箱的第一仓的像素，其中第一仓的像素与图像的第一部分相关联，并且向第一仓中呈现一个或 更多的像素位于图像的第一部分之外并且与多个箱的第二不同仓相关联。 该方法还包括将与第二仓相关联的一个或多个像素渲染到第二仓，使得一个或多个像素被渲染到第一仓和第二仓。
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