公开(公告)号：US20050173768A1

公开(公告)日：2005-08-11

申请号：US11041063

申请日：2005-01-21

申请人： Choong-Ho Lee ,  Dong-Gun Park ,  Jae-Man Youn ,  Chul Lee

发明人： Choong-Ho Lee ,  Dong-Gun Park ,  Jae-Man Youn ,  Chul Lee

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L31/062

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7854

摘要： A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.

摘要翻译： 鳍式FET结构采用负字线方案。 翅片FET的栅极采用掺杂有n +杂质的电极，不执行用于阈值电压控制的沟道掺杂，或者通过低密度执行沟道掺杂，从而显着提高了鳍式FET的特性。 半导体衬底形成为第一导电类型，并且第一导电类型的鳍有源区域从半导体衬底的上表面突出并连接到半导体衬底。 在半导体衬底上形成绝缘层，并且在翅片有源区的上部和侧壁形成栅极绝缘层。 在绝缘层和栅极绝缘层上形成栅电极。 源极和漏极形成在栅极两侧的鳍片有源区域中。

公开(公告)号：US20050170593A1

公开(公告)日：2005-08-04

申请号：US11046623

申请日：2005-01-28

申请人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

发明人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8228 ,  H01L29/786 ,  H01M8/00

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

摘要翻译： 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源极和漏极区域形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。