公开(公告)号：US09128023B2

公开(公告)日：2015-09-08

申请号：US13916273

申请日：2013-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Phillip Michel Nadeau ,  Baher S. Haroun ,  Srinath M. Ramaswamy

IPC: G01S7/40 ,  G01N22/00 ,  G01J3/28 ,  G01S7/41 ,  G01J3/42 ,  G01S7/00

CPC classification number: G01N22/00 ,  G01J3/28 ,  G01J3/42 ,  G01S7/40 ,  G01S7/41

Abstract: A technique for removing the background from a transmission spectrum including determining performance characteristics of a detector, measuring a transmission spectrum that includes an absorption line, determining performance characteristics of a gas cell, and removing a background spectrum from the transmission spectrum by combining the transmission spectrum with the performance characteristics of the detector and the performance characteristics of the gas cell.

Abstract translation: 一种用于从传输频谱中去除背景的技术，包括确定检测器的性能特征，测量包括吸收线的透射光谱，确定气体单元的性能特征，以及通过组合透射光谱来从透射光谱中去除背景光谱 具有检测器的性能特征和气室的性能特征。

公开(公告)号：US09075113B2

公开(公告)日：2015-07-07

申请号：US14230771

申请日：2014-03-31

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract translation: IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US09048728B2

公开(公告)日：2015-06-02

申请号：US13647156

申请日：2012-10-08

Applicant: Texas Instruments Incorporated

Inventor： Harikrishna Parthasarathy ,  Srinivas Venkata Veeramreddi ,  Sudhir Polarouthu ,  Baher S. Haroun

IPC: G05F1/63 ,  H02M3/156

CPC classification number: H02M3/1563

Abstract: Two hysteresis levels, a high level and a low level, may be used to set a period (and the switching frequency) of the output voltage of a DC-DC converter, as well as the output ripple of the converter. These two thresholds may be changed using pairs of switches. By controlling the sequence and the duration of the on-time of the switches, spectral spurs in the output can be controlled and the amplitude and the frequency band of interest can be reduced. Additional spur reduction may be possible by randomizing the control of the switches.

Abstract translation: 可以使用两个滞后电平（高电平和低电平）来设置DC-DC转换器的输出电压的周期（和开关频率）以及转换器的输出纹波。 这两个阈值可以使用成对的开关来改变。 通过控制开关的导通时间的顺序和持续时间，可以控制输出中的频谱杂散，并且可以减小感兴趣的幅度和频带。 通过对开关的控制进行随机化，可以实现额外的齿间减少。

公开(公告)号：US20140181608A1

公开(公告)日：2014-06-26

申请号：US14190314

申请日：2014-02-26

Applicant: Texas Instruments Incorporated

Inventor： Baher S. Haroun ,  Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

公开(公告)号：US08578225B2

公开(公告)日：2013-11-05

申请号：US13737474

申请日：2013-01-09

Applicant: Texas Instruments Incorporated

Inventor： Baher S. Haroun ,  Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract translation: 描述了用于在集成电路上测试多个电路的架构。 该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

公开(公告)号：US20130139017A1

公开(公告)日：2013-05-30

申请号：US13670078

申请日：2012-11-06

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

公开(公告)号：US20130124936A1

公开(公告)日：2013-05-16

申请号：US13737474

申请日：2013-01-09

Applicant: Texas Instruments Incorporated

Inventor： Baher S. Haroun ,  Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555 ,  G01R31/318558 ,  G11C29/46

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.