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    SEMICONDUCTOR MEMORY DEVICE
    101.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210050353A1

    公开(公告)日：2021-02-18

    申请号：US17089734

    申请日：2020-11-05

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Feng-Yi Chang ,  Fu-Che Lee

    IPC: H01L27/108 ,  H01L21/311 ,  H01L49/02

    Abstract: A semiconductor memory device and a method of forming the same are provided, with the semiconductor memory device including a substrate, a stacked structure, plural openings, plural flared portions and an electrode layer. The stacked structure is disposed on the substrate and includes alternately stacked oxide material layers and stacked nitride material layers. Each of the openings is disposed in the stacked structure, and each of the flared portions is disposed under each of the openings, in connection with each opening. The electrode layer is disposed on surfaces of each opening and each flared portion.

    Method of forming semiconductor memory device
    103.
    发明授权
    Method of forming semiconductor memory device 有权

    公开(公告)号：US10818664B2

    公开(公告)日：2020-10-27

    申请号：US16512306

    申请日：2019-07-15

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

    IPC: H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  G11C7/02 ,  G11C11/404

    Abstract: A method of forming semiconductor memory device, the semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.

    Semiconductor memory device and manufacturing method thereof
    104.
    发明授权
    Semiconductor memory device and manufacturing method thereof 有权

    公开(公告)号：US10777559B1

    公开(公告)日：2020-09-15

    申请号：US16361222

    申请日：2019-03-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Han Wu ,  Feng-Yi Chang ,  Fu-Che Lee ,  Wen-Chieh Lu

    IPC: H01L27/108

    Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.

    METHOD FOR FORMING SEMICONDUCTOR PATTERN
    106.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR PATTERN 审中-公开

    公开(公告)号：US20200212048A1

    公开(公告)日：2020-07-02

    申请号：US16258657

    申请日：2019-01-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Gang-Yi Lin ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Feng-Yi Chang ,  Ying-Chih Lin ,  Kai-Lou Huang ,  Yi-Ching Chang

    IPC: H01L27/108

    Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.

    CAPACITOR STRUCTURE
    107.
    发明申请
    CAPACITOR STRUCTURE 审中-公开

    公开(公告)号：US20200212042A1

    公开(公告)日：2020-07-02

    申请号：US16812384

    申请日：2020-03-09

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chieh-Te Chen

    IPC: H01L27/108 ,  H01L21/02 ,  H01L49/02 ,  H01L21/311

    Abstract: A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.

    Method of fabricating contact hole
    108.
    发明授权
    Method of fabricating contact hole 有权

    公开(公告)号：US10685868B2

    公开(公告)日：2020-06-16

    申请号：US16553202

    申请日：2019-08-28

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Hsin-Yu Chiang ,  Yu-Ching Chen

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/311

    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.

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