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公开(公告)号：US11038014B2
公开(公告)日：2021-06-15
申请号：US16154704
申请日：2018-10-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/76 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US10672612B2
公开(公告)日：2020-06-02
申请号：US15969788
申请日：2018-05-03
Inventor： Gang-Yi Lin , Feng-Yi Chang , Ying-Chih Lin , Fu-Che Lee
IPC: H01L21/033 , H01L21/311
Abstract: The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.
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公开(公告)号：US20200212048A1
公开(公告)日：2020-07-02
申请号：US16258657
申请日：2019-01-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Gang-Yi Lin , Shih-Fang Tzou , Fu-Che Lee , Feng-Yi Chang , Ying-Chih Lin , Kai-Lou Huang , Yi-Ching Chang
IPC: H01L27/108
Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
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公开(公告)号：US10795255B2
公开(公告)日：2020-10-06
申请号：US16175858
申请日：2018-10-31
Inventor： Wei-Lun Hsu , Gang-Yi Lin , Yu-Hsiang Hung , Ying-Chih Lin , Feng-Yi Chang , Ming-Te Wei , Shih-Fang Tzou , Fu-Che Lee , Chia-Liang Liao
IPC: G03F1/36 , H01L23/538 , G03F1/38 , H01L21/033 , H01L21/308 , G03F1/00 , G03F7/20 , G03F7/00 , H01L27/108
Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
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公开(公告)号：US10658178B2
公开(公告)日：2020-05-19
申请号：US16024907
申请日：2018-07-01
Inventor： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L21/311 , H01L21/033 , H01L21/027 , H01L27/108
Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.
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Patent Agency Ranking
公开(公告)号：US20200083325A1
公开(公告)日：2020-03-12
申请号：US16154704
申请日：2018-10-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/06 , H01L21/027 , H01L29/66 , H01L21/033 , H01L21/311 , H01L21/3213
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US10535530B2
公开(公告)日：2020-01-14
申请号：US16167435
申请日：2018-10-22
Inventor： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L21/308 , H01L21/033 , H01L21/8234
Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.
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公开(公告)号：US20190304777A1
公开(公告)日：2019-10-03
申请号：US15964031
申请日：2018-04-26
Inventor： Feng-Yi Chang , Fu-Che Lee , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L21/02 , H01L21/033
Abstract: The present invention provides a method for fabricating a hard mask, comprising: firstly, a first material layer and a second material layer are provided on the first material layer, a cell region and a peripheral region are defined thereon, and then a plurality of sacrificial patterns and a plurality of spacers are formed in the cell region on the second material layer, each two spacers are located at two sides of each of the sacrificial patterns. Afterwards, a first etching step is performed to remove the sacrificial patterns, a second etching step is performed to remove a portion of the second material layer and expose a portion of the first material layer within the cell region, and a third etching step is performed to remove portions of the first material layer, so as to forma plurality of first recesses in the first material layer.
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公开(公告)号：US20190172722A1
公开(公告)日：2019-06-06
申请号：US16158316
申请日：2018-10-12
Inventor： Feng-Yi Chang , Wei-Hsin Liu , Ying-Chih Lin , Jui-Min Lee , Gang-Yi Lin , Fu-Che Lee
IPC: H01L21/311 , H01L21/308 , H01L21/033 , H01L27/105
CPC classification number: H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L27/1052
Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.
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公开(公告)号：US11545547B2
公开(公告)日：2023-01-03
申请号：US17317912
申请日：2021-05-12
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/76 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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