公开(公告)号：US20070109265A1

公开(公告)日：2007-05-17

申请号：US11302711

申请日：2005-12-14

申请人： Tzu-Chiang Shih ,  Chih-Hung Lin

发明人： Tzu-Chiang Shih ,  Chih-Hung Lin

IPC分类号： G09G5/08

CPC分类号： G06F3/038 ,  G06F3/0383

摘要： A mouse with a multi-function button is provided. By using firmware, the scroll wheel signal and the button signal are simulated as the fourth button's information and the fifth button's information of a five-button mouse identifiable by the operation system. Consequently, no additional mouse driver for executing the functions of the fourth and fifth buttons is required when a three-button mouse is used.

摘要翻译： 提供具有多功能按钮的鼠标。 通过使用固件，将滚轮信号和按钮信号作为第四按钮的信息和第五按钮的操作系统可识别的五键鼠标的信息进行模拟。 因此，当使用三键鼠标时，不需要用于执行第四和第五按钮的功能的附加鼠标驱动器。

公开(公告)号：US06304119B1

公开(公告)日：2001-10-16

申请号：US09748926

申请日：2000-12-27

申请人： Huan-Ming Tseng ,  I-Shih Tseng ,  Chau-Chin Su ,  Chih-Hung Lin ,  Chun-Min Yang

发明人： Huan-Ming Tseng ,  I-Shih Tseng ,  Chau-Chin Su ,  Chih-Hung Lin ,  Chun-Min Yang

IPC分类号： H03L700

CPC分类号： H03L7/0805 ,  G01R31/3191 ,  G01R31/31922 ,  H03L7/07 ,  H03L7/0812

摘要： A timing generating apparatus includes a master timing module adapted to receive an external reference clock and to generate a coarse timing pulse signal. A slave timing module is coupled electrically to the master timing module and receives the coarse timing pulse signal, from which a fine timing pulse signal is generated. A calibration module coupled electrically to the master timing module and the slave timing module receives the coarse timing pulse signal and the fine timing pulse signal, determines a phase difference value between the two, and generates a phase compensation signal corresponding to difference between the phase difference value and a predetermined phase difference value. The slave timing module includes a delay control unit and a voltage-controlled delay unit, which introduce a phase delay into the coarse timing pulse signal so as to generate the fine timing pulse signal.

摘要翻译： 定时产生装置包括适于接收外部参考时钟并产生粗定时脉冲信号的主定时模块。 从时序模块电耦合到主定时模块，并接收粗定时脉冲信号，从而产生精细定时脉冲信号。 与主定时模块和从定时模块电连接的校准模块接收粗定时脉冲信号和精细定时脉冲信号，确定两者之间的相位差值，并产生对应于相位差之间的差的相位补偿信号 值和预定的相位差值。 从时序模块包括延迟控制单元和压控延迟单元，其将相位延迟引入到粗定时脉冲信号中，以产生精细定时脉冲信号。

公开(公告)号：US06194271B1

公开(公告)日：2001-02-27

申请号：US09237295

申请日：1999-01-25

申请人： Chih-Hung Lin ,  Joe Ko

发明人： Chih-Hung Lin ,  Joe Ko

IPC分类号： H01L218247

CPC分类号： H01L27/11521

摘要： A method of fabricating a flash memory. A gate is formed on a provided substrate. A first doping process is performed. A patterned mask layer is formed over the substrate. A shallow trench isolation structure is formed in the substrate by using the gate and the mask layer as a mask. A portion of the substrate defined below the gate is a first active region and a portion of the substrate defined below the mask layer is a second active region. The mask layer is removed. A dielectric layer and a conductive layer are formed in sequence over the substrate. The conductive layer, the dielectric layer and the gate are patterned to form a control gate and a floating gate, wherein a portion of the control gate overlap with the second active region. A second doping process is performed.

摘要翻译： 一种制造闪速存储器的方法。 栅极形成在所提供的衬底上。 执行第一掺杂过程。 在衬底上形成图案化掩模层。 通过使用栅极和掩模层作为掩模在衬底中形成浅沟槽隔离结构。 位于栅极下方的衬底的一部分是第一有源区，并且限定在掩模层下面的衬底的一部分是第二有源区。 去除掩模层。 在衬底上依次形成电介质层和导电层。 将导电层，电介质层和栅极图案化以形成控制栅极和浮置栅极，其中控制栅极的一部分与第二有源区域重叠。 执行第二掺杂过程。

公开(公告)号：US6001707A

公开(公告)日：1999-12-14

申请号：US241760

申请日：1999-02-01

申请人： Chih-Hung Lin ,  Gary Hong

发明人： Chih-Hung Lin ,  Gary Hong

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

摘要翻译： 在衬底中形成浅沟槽隔离结构的方法包括以下步骤：在沟槽的未来顶角区域周围形成掺杂区域。 掺杂区内掺杂剂的浓度朝向衬底表面增加。 之后，在衬底中形成沟槽，然后进行热氧化操作。 利用掺杂衬底相对于未掺杂区域的较高氧化速率，沟槽的上角变成圆角。 随后，使用常规方法在沟槽内的衬底表面上形成衬里氧化物层。 最后，将绝缘材料沉积到沟槽中以形成沟槽隔离结构。

公开(公告)号：US5891783A

公开(公告)日：1999-04-06

申请号：US927323

申请日：1997-09-11

申请人： Chih-Hung Lin ,  Jih-Wen Chou

发明人： Chih-Hung Lin ,  Jih-Wen Chou

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66583 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/7833

摘要： A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed. A undoped silicate glass layer and a borophosphosilicate layer are formed in sequence, and an air gap is formed between the suspended part of the poly-gate and the substrate.

摘要翻译： 一种降低半导体器件中栅极和衬底之间的条纹电容的方法。 在其上具有缓冲氧化物层的衬底上形成氮化硅并且被图案化以形成开口。 去除开口内的缓冲氧化物层，并且在与栅极氧化物层相同的位置处形成另一氧化物层。 在开口处形成具有比开口宽的宽度的多门。 因此，两端的多晶硅栅极的一部分覆盖氮化硅层的一部分。 然后去除氮化硅层，并将多晶硅栅极留作T形，其两端悬在衬底上。 以大角度，将光掺杂剂注入到多晶硅栅极的悬置部分之下的衬底中以形成轻掺杂区域。 在另一个更小的角度，重掺杂剂被注入到多晶硅栅极旁边的衬底中。 因此，形成源极/漏极。 依次形成未掺杂的硅酸盐玻璃层和硼磷硅酸盐层，并且在多晶硅的悬浮部分和基板之间形成气隙。