公开(公告)号：US20120290782A1

公开(公告)日：2012-11-15

申请号：US13555908

申请日：2012-07-23

Applicant: Dinesh Maheshwari

Inventor： Dinesh Maheshwari

IPC: G06F12/00

CPC classification number: G11C29/816 ,  G11C15/00

Abstract: A method of mapping logical block select signals to physical blocks can include receiving at least one signal for each of n+1 logical blocks, where n is an integer greater than one, that each map to one of m+1 physical blocks, where n

Abstract translation: 将逻辑块选择信号映射到物理块的方法可以包括为n + 1个逻辑块中的每一个接收至少一个信号，其中n是大于1的整数，每个映射到m + 1个物理块之一，其中n

公开(公告)号：US08266373B1

公开(公告)日：2012-09-11

申请号：US11000568

申请日：2004-11-30

Applicant: Scott Smith

Inventor： Scott Smith

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A content addressable memory (CAM) can include a CAM memory array having both a data field and a mask field. A multiplexer (MUX) can selectively load data from either a register or an external data input to one or both fields of the CAM memory array.

Abstract translation: 内容可寻址存储器（CAM）可以包括具有数据字段和掩码字段两者的CAM存储器阵列。 复用器（MUX）可以选择性地将来自寄存器或外部数据输入的数据加载到CAM存储器阵列的一个或两个场。

公开(公告)号：US08214305B1

公开(公告)日：2012-07-03

申请号：US12313868

申请日：2008-11-24

Applicant: Mark Birman ,  Andrew Rosman ,  Pankaj Gupta ,  Ashish Goel

Inventor： Mark Birman ,  Andrew Rosman ,  Pankaj Gupta ,  Ashish Goel

IPC: G06F15/18

CPC classification number: G06F17/30982

Abstract: A data stream search system can include a plurality of search data inputs logically divided into at least M+N sets. The sets have a logical order with respect to one another, each set providing more than one bit value. A key application circuit can comprise a plurality of data paths that each couple a different group of at least M data input sets to a corresponding content addressable memory (CAM) section. Each different group of at least M data input sets can be contiguous with respect to the logical order, and shifted in bit order from one another by at least two bits.

Abstract translation: 数据流搜索系统可以包括逻辑上划分为至少M + N个集合的多个搜索数据输入。 这些集合相对于彼此具有逻辑顺序，每个集合提供多于一个比特值。 密钥应用电路可以包括多个数据路径，每个数据路径将至少M个数据输入集合的不同组耦合到相应的内容可寻址存储器（CAM）部分。 至少M个数据输入集合的每个不同的组可以相对于逻辑顺序是连续的，并且以比特顺序从彼此移位至少两个比特。

公开(公告)号：US08196017B1

公开(公告)日：2012-06-05

申请号：US11983382

申请日：2007-11-07

Applicant: Pankaj Gupta

Inventor： Pankaj Gupta

IPC: G11C29/00

CPC classification number: G11C15/00 ,  G06F11/1068 ,  G11C2029/0409 ,  G11C2207/104

Abstract: A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correction, the entries can be searched by applying an appended key value that includes a key portion (KEY) and replicated key portion (KEY(REP)).

Abstract translation: CAM系统（200）可以包括具有用于存储数据值（例如，E1）的一部分和用于存储复制数据值（E1（REP））的另一部分的多个条目（202-0至202-3）。 对于即时纠错，可以通过应用包括密钥部分（KEY）和复制密钥部分（KEY（REP））的附加密钥值来搜索条目。

公开(公告)号：US08185689B1

公开(公告)日：2012-05-22

申请号：US12901886

申请日：2010-10-11

Applicant: Vinay Raja Iyengar ,  Venkat Rajendher Reddy Gaddam ,  Aparna Bharat

Inventor： Vinay Raja Iyengar ,  Venkat Rajendher Reddy Gaddam ,  Aparna Bharat

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F17/30982

Abstract: A method may include, in response to a single command and an N-bit segment value, generating a search key comprising M segments for at least one of a plurality of different databases, the N-bit segment value forming different ones of the M search key segments according to a database configuration of the at least one database.

Abstract translation: 一种方法可以包括响应于单个命令和N位分段值，生成包含多个不同数据库中的至少一个的M个分段的搜索关键字，形成不同的M个搜索的N比特分段值 根据所述至少一个数据库的数据库配置的关键段。

公开(公告)号：US08086641B1

公开(公告)日：2011-12-27

申请号：US12336565

申请日：2008-12-17

Applicant: David Walter Carr

Inventor： David Walter Carr

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/30327

Abstract: An integrated search engine device evaluates span prefix masks for keys residing at leaf parent levels of a search tree to identify a longest prefix match to an applied search key. This longest prefix match resides at a leaf node of the search tree that is outside a search path of the search tree for the applied search key. The search engine device is also configured to read a bitmap associated with the leaf node to identify a pointer to associated data for the longest prefix match. The pointer has a value that is based on a position of a set bit within the bitmap that corresponds to a set bit within the span prefix mask that signifies the longest prefix match.

Abstract translation: 集成搜索引擎设备评估驻留在搜索树的叶父级别的密钥的跨度前缀掩码，以标识与应用的搜索关键字的最长前缀匹配。 该最长的前缀匹配位于搜索树的叶节点处，该搜索树位于搜索树的搜索路径之外，用于所应用的搜索关键字。 搜索引擎设备还被配置为读取与叶节点相关联的位图，以识别用于最长前缀匹配的关联数据的指针。 该指针具有基于位图内的设置位的位置的值，其对应于跨度前缀掩码内的表示最长前缀匹配的集合位。

公开(公告)号：US08054873B2

公开(公告)日：2011-11-08

申请号：US11724816

申请日：2007-03-15

Applicant: Joseph N. Babanezhad

Inventor： Joseph N. Babanezhad

IPC: H03H7/30

CPC classification number: H04B3/235

Abstract: A method and apparatus for joint training of an analog equalizer (AEQ) and an analog echo canceller (AEC) is described. In one embodiment, which both the AEQ and AEC process an input analog signal in the analog domain. In one embodiment, the method includes joint training the AEQ and the AEC using independent analog error signals.

Abstract translation: 描述了用于模拟均衡器（AEQ）和模拟回声消除器（AEC）的联合训练的方法和装置。 在一个实施例中，AEQ和AEC都在模拟域中处理输入模拟信号。 在一个实施例中，该方法包括使用独立的模拟误差信号联合训练AEQ和AEC。

公开(公告)号：US08023299B1

公开(公告)日：2011-09-20

申请号：US12730184

申请日：2010-03-23

Applicant: Nilesh A. Gharia

Inventor： Nilesh A. Gharia

IPC: G11C15/00

CPC classification number: G11C15/02 ,  G11C11/16 ,  G11C15/046

Abstract: A CAM device includes an array of CAM cells each having a spin torque transfer (STT) storage cell to store a data bit. Each STT storage cell includes a first magnetic tunnel junction (MTJ) element coupled between a first input node and an output node of the CAM cell, a second MTJ element coupled between a second input node and the output node of the CAM cell, and a first match transistor coupled between the match line and ground potential and having a gate coupled to the output node. The logic state of the data bit is represented by the relative resistances of the first and second MTJ elements.

Abstract translation: CAM设备包括每个具有自旋转矩传输（STT）存储单元以存储数据位的CAM单元的阵列。 每个STT存储单元包括耦合在第一输入节点和CAM单元的输出节点之间的第一磁隧道结（MTJ）元件，耦合在第二输入节点和CAM单元的输出节点之间的第二MTJ元件，以及 第一匹配晶体管耦合在匹配线和地电位之间，并且具有耦合到输出节点的栅极。 数据位的逻辑状态由第一和第二MTJ元件的相对电阻表示。

公开(公告)号：US07995596B2

公开(公告)日：2011-08-09

申请号：US12120082

申请日：2008-05-13

Applicant: Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

Inventor： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L49/901 ,  H04L49/9021 ,  H04L49/9042 ,  H04L69/02 ,  H04L69/22 ,  H04L69/26

Abstract: A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.

Abstract translation: 提供了一种从软件中卸载数据包协议封装的方法。 在操作中，接收指针信息。 此外，使用指针信息，通过在硬件中组装分组，从软件卸载分组协议封装。

公开(公告)号：US07961723B2

公开(公告)日：2011-06-14

申请号：US10930456

申请日：2004-08-31

Applicant: David T. Hass

Inventor： David T. Hass

IPC: H04L12/28

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/30

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。