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公开(公告)号：US11677648B2
公开(公告)日：2023-06-13
申请号：US17182914
申请日：2021-02-23
Applicant: STMicroelectronics Application GMBH
Inventor： Fred Rennig
CPC classification number: H04L43/08 , H04L12/40 , H04L2012/40215
Abstract: In accordance with an embodiment, a method includes determining whether a frame received from a communication bus is encoded according to a particular communication protocol and is addressed to a particular electronic device; increasing a frame count value when the frame is encoded according to the particular communication protocol and is addressed to the particular electronic device based on the determination, wherein increasing the frame count value comprises increasing a count of a modular arithmetic counter circuit having a first bit depth, and the frame count value is constrained to a modulus value of the modular arithmetic counter circuit; setting a frame count status bit based on comparing the frame count value to threshold values, and transmitting a frame comprising the frame counter status bit over the communication bus, and resetting the frame count value at an end of a monitoring time interval.
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公开(公告)号：US11675721B2
公开(公告)日：2023-06-13
申请号：US17806587
申请日：2022-06-13
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , G05B19/042 , G06F9/54 , H04L12/403 , H03M13/09
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F13/4068 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US20230013396A1
公开(公告)日：2023-01-19
申请号：US17933680
申请日：2022-09-20
Applicant: STMicroelectronics Application GMBH
Inventor： Rolf Nandlinger
IPC: G06F1/14
Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.
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公开(公告)号：US11474752B2
公开(公告)日：2022-10-18
申请号：US16932426
申请日：2020-07-17
Applicant: STMicroelectronics Application GmbH
Inventor： Roberto Colombo
Abstract: A processing system comprises a processing unit, a hardware block configured to change operation as a function of life cycle data, and a one-time programmable memory storing original life cycle data. A hardware configuration module is configured to read the original life cycle data from the one-time programmable memory, to store the original life cycle data in a register, to receive a write request from the processing unit, and to selectively execute the write request to overwrite the original life cycle data with new life cycle data in the register.
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公开(公告)号：US20220312566A1
公开(公告)日：2022-09-29
申请号：US17654532
申请日：2022-03-11
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S. r. l. , STMicroelectronics Application GMBH
Inventor： Manuel Gaertner , Philippe Sirito-Olivier , Giovanni Luca Torrisi , Thomas Urbitsch , Christophe Roussel , Fritz Burkhardt
IPC: H05B45/46 , H05B45/325 , H05B45/50 , H05B45/14
Abstract: A system includes lighting devices coupled to output supply pins, a microcontroller circuit, and a driver circuit, which receives data therefrom, and switches coupled in series to the lighting devices. The driver circuit includes output supply pins and selectively propagates a supply voltage to the output supply pins to provide respective pulse-width modulated supply signals at the output supply pins. The driver circuit computes duty-cycle values of the pulse-width modulated supply signals as a function of the data received from the microcontroller circuit. The lighting devices include at least one subset coupled to the same output supply pin. The microcontroller individually controls the switches via respective control signals to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices.
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Patent Agency Ranking
公开(公告)号：US20220286319A1
公开(公告)日：2022-09-08
申请号：US17677113
申请日：2022-02-22
Inventor： Fred Rennig , Vaclav Dvorak
IPC: H04L12/403 , G06F9/30
Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.
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公开(公告)号：US11366778B2
公开(公告)日：2022-06-21
申请号：US16874055
申请日：2020-05-14
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , H04L12/403 , G05B19/042 , H03M13/09
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US11360143B2
公开(公告)日：2022-06-14
申请号：US17083876
申请日：2020-10-29
Applicant: STMicroelectronics International N.V. , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
Inventor： Avneep Kumar Goyal , Deepak Baranwal , Thomas Szurmant , Nicolas Bernard Grossier
IPC: G01R31/317 , G01R31/3185 , G01R31/3193 , G06F11/34 , G01R31/319 , G06F11/36
Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.
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公开(公告)号：US11210161B2
公开(公告)日：2021-12-28
申请号：US16928768
申请日：2020-07-14
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
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公开(公告)号：US20210357538A1
公开(公告)日：2021-11-18
申请号：US17443497
申请日：2021-07-27
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Giovanni Disirio
IPC: G06F21/83 , G06F21/64 , G06F12/02 , G06F9/38 , G06F9/445 , H04L9/32 , G06F21/57 , G09C1/00 , G06F21/74 , H04W12/106
Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
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