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公开(公告)号：US12184448B2
公开(公告)日：2024-12-31
申请号：US18489590
申请日：2023-10-18
Inventor： Vaclav Dvorak , Fred Rennig
Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.
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公开(公告)号：US11853252B2
公开(公告)日：2023-12-26
申请号：US17819749
申请日：2022-08-15
Inventor： Fred Rennig , Vaclav Dvorak
CPC classification number: G06F13/4282 , G06F9/30134 , G06F13/28 , G06F13/4072
Abstract: A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.
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公开(公告)号：US20230053798A1
公开(公告)日：2023-02-23
申请号：US17819749
申请日：2022-08-15
Inventor： Fred Rennig , Vaclav Dvorak
Abstract: A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.
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公开(公告)号：US20170178734A1
公开(公告)日：2017-06-22
申请号：US15244664
申请日：2016-08-23
Inventor： Marco Pasotti , Fabio De Santis , Roberto Bregoli , Dario Livornesi , Sandor Petenyi
IPC: G11C16/30 , G11C5/14 , G11C16/04 , H01L27/115 , G11C16/28
CPC classification number: G11C16/30 , G05F3/30 , G11C5/147 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/28 , G11C2216/10 , H01L27/11521 , H01L27/1156 , H03F3/45188 , H03F3/45475 , H03F2200/456 , H03F2203/45341 , H03F2203/45342 , H03F2203/45528 , H03F2203/45674 , H03F2203/45676
Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.
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公开(公告)号：US20230267087A1
公开(公告)日：2023-08-24
申请号：US18309103
申请日：2023-04-28
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , H04L12/403 , G05B19/042 , G06F9/54
CPC classification number: G06F13/362 , G06F13/4068 , G06F11/0772 , G06F11/0739 , H04L12/403 , G06F11/0757 , G05B19/042 , G06F9/542 , H03M13/09
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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Patent Agency Ranking
公开(公告)号：US20220318173A1
公开(公告)日：2022-10-06
申请号：US17806587
申请日：2022-06-13
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , H04L12/403 , G05B19/042
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US20240362176A1
公开(公告)日：2024-10-31
申请号：US18764940
申请日：2024-07-05
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G05B19/042 , G06F9/54 , G06F11/07 , G06F11/10 , G06F13/40 , G06F13/42 , H03M13/09 , H04L12/40 , H04L12/403
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F11/1004 , G06F13/4068 , G06F13/4282 , H04L12/40006 , H04L12/40013 , H04L12/40078 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09 , H04L2012/40215
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US11675721B2
公开(公告)日：2023-06-13
申请号：US17806587
申请日：2022-06-13
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G06F13/40 , G06F11/07 , G05B19/042 , G06F9/54 , H04L12/403 , H03M13/09
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F13/4068 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US12066962B2
公开(公告)日：2024-08-20
申请号：US18309103
申请日：2023-04-28
Inventor： Fred Rennig , Ludek Beran
IPC: G06F13/362 , G05B19/042 , G06F9/54 , G06F11/07 , G06F11/10 , G06F13/40 , G06F13/42 , H04L12/40 , H04L12/403 , H03M13/09
CPC classification number: G06F13/362 , G05B19/042 , G06F9/542 , G06F11/0739 , G06F11/0757 , G06F11/0772 , G06F11/1004 , G06F13/4068 , G06F13/4282 , H04L12/40006 , H04L12/40013 , H04L12/40078 , H04L12/403 , G05B2219/1215 , G05B2219/2231 , G05B2219/31179 , H03M13/09 , H04L2012/40215
Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.
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公开(公告)号：US20240048405A1
公开(公告)日：2024-02-08
申请号：US18489590
申请日：2023-10-18
Inventor： Vaclav Dvorak , Fred Rennig
CPC classification number: H04L12/40013 , G06F13/423 , H04L12/40169 , H04L2012/40215
Abstract: In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.
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