公开(公告)号：US06288419B1

公开(公告)日：2001-09-11

申请号：US09350687

申请日：1999-07-09

Applicant: Kirk D. Prall ,  Pai-Hung Pan

Inventor： Kirk D. Prall ,  Pai-Hung Pan

IPC: H01L2976

CPC classification number: H01L21/28273 ,  H01L29/42324

Abstract: Floating gate stacks having a metal control gate and a polysilicon floating gate and their methods of fabrication that are particularly useful for floating gate memory cells and apparatus produced therefrom. The metal control gate permits reduced gate resistance and gate height over polysilicon or silicide control gates. An oxidation barrier is formed on sidewalls of the metal control gate to protect it from oxidation during oxidation of sidewalls of the polysilicon floating gate. The oxidation barrier is useful in reducing peeling, stress and related oxidation problems when using metals such as tungsten in the metal control gate.

Abstract translation: 具有金属控制栅极和多晶硅浮动栅极的浮栅堆叠及其制造方法对于浮栅存储器单元及其制造的设备特别有用。 金属控制栅极允许在多晶硅或硅化物控制栅极上降低栅极电阻和栅极高度。 在金属控制栅极的侧壁上形成氧化屏障，以防止在多晶硅浮动栅极的侧壁氧化期间氧化。 当在金属控制门中使用诸如钨的金属时，氧化屏障可用于减少剥离，应力和相关的氧化问题。

公开(公告)号：US5945726A

公开(公告)日：1999-08-31

申请号：US766659

申请日：1996-12-16

Applicant: Kirk D. Prall ,  Mike P. Violette

Inventor： Kirk D. Prall ,  Mike P. Violette

IPC: H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/082 ,  H01L29/735

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/082 ,  H01L29/735

Abstract: A substantially concentric lateral bipolar transistor having a base region that is disposed about a periphery of an emitter region, and a collector region that is disposed about a periphery of the base region to form the concentric lateral bipolar transistor of the invention. A gate overlies the substrate and at least a portion of the base region. At least one electrical contact is formed connecting the base and the gate, although a plurality of contacts may be formed. A further bipolar transistor is formed according to the following method of the invention. A base region is formed in a substrate and a gate region is formed overlying at least a portion of the base region. Emitter and collector terminals are formed on opposed sides of the base region. The gate is used as a mask during first and second ion implants. During the first ion implant the ions bombard the substrate from a first direction to grade a base/emitter junction, and during the second ion implant ions bombard the substrate from a second direction to grade a base/collector junction. Also a lateral bipolar transistor having a decreased base width as a result of implanting ions after fabrication of collector and emitter regions to enlarge the collector and emitter regions, thereby decreasing the base region and increasing gain.

Abstract translation: 具有围绕发射极区域的周边设置的基极区域的基本上同心的横向双极晶体管，以及围绕所述基极区域的周边设置的集电极区域，以形成本发明的同心横向双极晶体管。 栅极覆盖衬底和基极区域的至少一部分。 形成连接基座和栅极的至少一个电触头，尽管可以形成多个触点。 根据本发明的以下方法形成另外的双极晶体管。 在基板中形成基极区域，并且形成覆盖基极区域的至少一部分的栅极区域。 发射极和集电极端子形成在基极区域的相对侧上。 在第一和第二离子注入期间，门用作掩模。 在第一离子注入期间，离子从第一方向轰击衬底以分级基极/发射极结，并且在第二离子注入期间，离子从第二方向轰击衬底以对基极/集电极结进行分级。 另外，作为在集电极和发射极区域制造之后注入离子的结果，具有减小的基极宽度的横向双极晶体管，以扩大集电极和发射极区域，从而减小基极区域并增加增益。

公开(公告)号：US5605864A

公开(公告)日：1997-02-25

申请号：US285335

申请日：1994-08-02

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/44 ,  H01L21/48

CPC classification number: H01L27/10852 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S438/947

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a DRAM cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that if fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. Etching of the spacer creates a buried contact opening smaller than lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after resist strip leaving a sublithographic buried contact opening.

Abstract translation: 使用可去除的氧化物间隔物来减小在低于光刻最小值的多晶硅字线之间的DRAM单元中的接触开口的尺寸。 可去除的间隔物在掩埋接触图案化和蚀刻之前被沉积。 由于字线在单元位置发散，所以可拆卸间隔物在发散区域接触开口之间保持较小的厚度，并且由于其间较窄的间隙而在字线之间的其他位置具有更大的厚度，并且间隔物被沉积，使得如果填充间隙。 由于实际的自对准接触区域由间隔壁侧壁限定，所以可拆卸间隔物减小了埋入接触尺寸。 间隔物的蚀刻产生小于光刻最小值的埋入接触开口，因为围绕埋入接触区域的氧化硅被可移除间隔物保护。 在抗蚀剂条带离开亚光刻掩埋的接触开口之后，去除可移除的间隔物。

公开(公告)号：US5488011A

公开(公告)日：1996-01-30

申请号：US336426

申请日：1994-11-08

Applicant: Thomas A. Figura ,  Kirk D. Prall

Inventor： Thomas A. Figura ,  Kirk D. Prall

IPC: H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method of forming a contact area between two vertical structures. A first layer of material conforming to an extending between vertical sidewalls is covered with a mask layer. The mask layer is patterned and etched to remove the horizontal region of the mask layer between the vertical sidewalls, thereby exposing the first layer of material at the desired location of the contact area, while retaining at least a portion of the vertical regions of the mask layer. Using the remaining vertical regions of the mask layer as etch mask, the exposed portions of the first layer are then etched away to form the contact area. Another aspect of the invention provides a method of making a DRAM that utilizes a capacitor insulating layer over the capacitor second conductor (or cell poly) to self-align the bit line contact to the capacitor second conductor. In accordance with this aspect of the invention, a capacitor is formed over a semiconductor wafer. The capacitor includes a first conductor, a dielectric layer on the first conductor and a second conductor on the dielectric layer. A capacitor insulating layer is formed on the second conductor. The capacitor insulating layer is patterned and etched to expose portions of the second conductor at the desired location of the bit line contact. Then, using the capacitor insulating layer as a hard mask, the exposed portions of the second conductor are etched away in the area in which the bit line contact will subsequently be formed.

Abstract translation: 一种在两个垂直结构之间形成接触区域的方法。 符合在垂直侧壁之间延伸的第一材料层被掩模层覆盖。 掩模层被图案化和蚀刻以去除垂直侧壁之间的掩模层的水平区域，从而将第一层材料暴露在接触区域的期望位置处，同时保留掩模的垂直区域的至少一部分 层。 使用掩模层的其余垂直区域作为蚀刻掩模，然后蚀刻掉第一层的暴露部分以形成接触面积。 本发明的另一方面提供了一种制造DRAM的方法，该DRAM利用电容器第二导体（或电池多晶硅）上的电容绝缘层将位线接触自对准到电容器第二导体。 根据本发明的该方面，在半导体晶片上形成电容器。 电容器包括第一导体，第一导体上的电介质层和介电层上的第二导体。 在第二导体上形成电容绝缘层。 对电容器绝缘层进行图案化和蚀刻，以在位线接触的期望位置处露出第二导体的部分。 然后，使用电容器绝缘层作为硬掩模，在随后将形成位线接触的区域中蚀刻掉第二导体的暴露部分。

公开(公告)号：US5281548A

公开(公告)日：1994-01-25

申请号：US920793

申请日：1992-07-28

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L29/788 ,  H01L21/76 ,  H01L27/115

CPC classification number: H01L29/7885

Abstract: A device and a method of forming a floating gate memory transistor of very small area, thereby allowing a high-density integrated circuit chip, more specifically for Erasable Programmable Read-Only Memory (EPROM) or similar non-volatile devices.In a first embodiment, a method is disclosed that fabricates a programmable memory cell described as a "diffusion cut" cell where a plug-type floating gate contact hole cuts through a diffusion region and partially into a substrate region. In a second embodiment, a method is disclosed that fabricates a programmable memory cell described as an "oxide cut" cell, where the plug-type floating gate contact hole only penetrates a silicon oxide layer. This "oxide cut" cell is formed in a similar fashion except penetration does not go into the diffusion region or substrate.

Abstract translation: 一种形成非常小面积的浮动栅极存储晶体管的器件和方法，从而允许高密度集成电路芯片，更具体地说可用于可擦除可编程只读存储器（EPROM）或类似的非易失性器件。 在第一实施例中，公开了一种制造被描述为“扩散切割”单元的可编程存储器单元的方法，其中插头式浮栅接触孔穿过扩散区并且部分地切入衬底区域。 在第二实施例中，公开了一种制造被描述为“氧化物切割”电池的可编程存储器单元的方法，其中插塞式浮栅接触孔仅穿透氧化硅层。 这种“氧化物切割”电池以类似的方式形成，除了渗透不会进入扩散区域或衬底。