专利检索 cpc:"H01L21/8222" 第 1 页

1.

发明授权
Method for producing a diode 有权

公开(公告)号：US11984360B2

公开(公告)日：2024-05-14

申请号：US17728088

申请日：2022-04-25

申请人： STMicroelectronics (Crolles 2) SAS

发明人： Gregory Avenier , Alexis Gauthier , Pascal Chevalier

IPC分类号： H01L21/82 , H01L21/3105 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L29/66 , H01L29/737 , H01L29/93

CPC分类号： H01L21/8222 , H01L21/31056 , H01L21/8249 , H01L27/0664 , H01L29/66174 , H01L29/66242 , H01L29/7371 , H01L29/93

摘要： A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.

2.

发明授权
Deep trench capacitor fuse structure for high voltage breakdown defense and methods for forming the same 有权

公开(公告)号：US11923355B2

公开(公告)日：2024-03-05

申请号：US17461133

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang

IPC分类号： H01L27/02 , H01L21/8222 , H01L21/8234 , H01L23/522 , H01L49/02

CPC分类号： H01L27/0248 , H01L21/8222 , H01L21/823475 , H01L23/5226 , H01L28/87 , H01L28/91

摘要： Devices and methods for manufacturing a deep trench capacitor fuse for high voltage breakdown defense. A semiconductor device comprising a deep trench capacitor structure and a transistor structure. The transistor structure may comprise a base, a first terminal formed within the base, and a second terminal formed within the base. The first terminal and the second terminal may be formed by doping the base. The deep trench capacitor structure may comprise a first metallic electrode layer and a second metallic electrode layer. The first terminal may be electrically connected to the first metallic electrode layer, and the second terminal may be electrically connected to the second metallic electrode layer.

3.

发明授权
III-N multichip modules and methods of fabrication 有权

公开(公告)号：US11908687B2

公开(公告)日：2024-02-20

申请号：US17563968

申请日：2021-12-28

申请人： Intel Corporation

发明人： Khaled Ahmed , Anup Pancholi , John Heck , Thomas Sounart , Harel Frish , Sansaptak Dasgupta

IPC分类号： H01L21/00 , H01L21/02 , H01L21/8234 , H01L21/8222

CPC分类号： H01L21/02458 , H01L21/02389 , H01L21/02452 , H01L21/8222 , H01L21/823418

摘要： A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

4.

发明公开
APPARATUS WITH VOLTAGE PROTECTION MECHANISM 审中-公开

公开(公告)号：US20240038759A1

公开(公告)日：2024-02-01

申请号：US18375048

申请日：2023-09-29

申请人： Micron Technology, Inc.

发明人： James E. Davis , Milind Nemchand Furia , Michael D. Chaine , Eric J. Smith

IPC分类号： H01L27/02 , H01L21/8222 , G11C16/30 , G11C5/14

CPC分类号： H01L27/0262 , H01L21/8222 , G11C16/30 , G11C5/14 , G11C16/0483

摘要： An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

5.

发明授权
Integrated circuit including transistors having a common base 有权

公开(公告)号：US11882707B2

公开(公告)日：2024-01-23

申请号：US17559821

申请日：2021-12-22

申请人： STMicroelectronics (Rousset) SAS

发明人： Philippe Boivin

IPC分类号： H10B63/00 , H01L21/8222 , H01L27/082 , H01L29/10 , H10N70/20 , H10N70/00

CPC分类号： H10B63/32 , H01L21/8222 , H01L27/0823 , H01L29/1004 , H10B63/80 , H10N70/231 , H10N70/826

摘要： The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.

6.

发明申请
FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS 有权

公开(公告)号：US20170365695A1

公开(公告)日：2017-12-21

申请号：US15187860

申请日：2016-06-21

申请人： GLOBALFOUNDRIES INC.

发明人： Vibhor Jain , Qizhi Liu

IPC分类号： H01L29/737 , H01L21/8228 , H01L21/8226 , H01L29/04 , H03F3/213 , H01L21/8222 , H01L29/165 , H01L29/161 , H01L27/082 , H01L29/66

CPC分类号： H01L29/7378 , H01L21/8222 , H01L21/8226 , H01L21/82285 , H01L21/8249 , H01L27/0623 , H01L27/0823 , H01L27/0826 , H01L29/04 , H01L29/0817 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66272 , H01L29/66287 , H01L29/7322 , H01L29/7371 , H03F3/213 , H03F2200/294

摘要： Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

7.

发明授权
Fabrication of integrated circuit structures for bipolor transistors 有权

公开(公告)号：US09847408B1

公开(公告)日：2017-12-19

申请号：US15187860

申请日：2016-06-21

申请人： GLOBALFOUNDRIES INC.

发明人： Vibhor Jain , Qizhi Liu

IPC分类号： H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/66 , H01L29/737 , H01L29/161 , H01L29/165 , H01L29/04 , H01L21/8222 , H03F3/213 , H01L21/8226

CPC分类号： H01L29/7378 , H01L21/8222 , H01L21/8226 , H01L21/82285 , H01L21/8249 , H01L27/0623 , H01L27/0823 , H01L27/0826 , H01L29/04 , H01L29/0817 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/161 , H01L29/165 , H01L29/66242 , H01L29/66272 , H01L29/66287 , H01L29/7322 , H01L29/7371 , H03F3/213 , H03F2200/294

摘要： Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.

8.

发明授权
Semiconductor device having field plate disposed on isolation feature and method for forming the same 有权

公开(公告)号：US09666699B1

公开(公告)日：2017-05-30

申请号：US15085219

申请日：2016-03-30

申请人： Vanguard International Semiconductor Corporation

发明人： Pei-Heng Hung , Manoj Kumar , Hsiung-Shih Chang , Chia-Hao Lee , Jun-Wei Chen

IPC分类号： H01L29/735 , H01L29/73 , H01L29/06 , H01L29/417 , H01L29/66 , H01L21/8222 , H01L21/762 , H01L29/423 , H01L29/40 , H01L29/861

CPC分类号： H01L29/7302 , H01L21/76264 , H01L21/8222 , H01L29/0649 , H01L29/402 , H01L29/41708 , H01L29/42304 , H01L29/6609 , H01L29/66128 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/861 , H01L29/8611

摘要： The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.