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公开(公告)号：US20210336065A1
公开(公告)日：2021-10-28
申请号：US16343485
申请日：2018-11-02
Inventor： Yanqing CHEN , Jianyun XIE , Wei LI , Cheng LI , Pan GUO , Yanfeng LI , Weida QIN , Ning WANG
IPC: H01L29/786 , H01L27/12 , H01L23/552
Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.
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公开(公告)号：US20210296365A1
公开(公告)日：2021-09-23
申请号：US17206254
申请日：2021-03-19
Inventor： Jun LIU , Liangchen YAN , Bin ZHOU , Yang ZHANG , Tongshang SU , Wei LI , Liusong NI
IPC: H01L27/12
Abstract: A display substrate, a method for forming the display substrate and a display device are provided. The display substrate includes: a first conductive pattern located on a base substrate, where a ring-shaped conductive protection structure is arranged at an edge of a preset region of the first conductive pattern and surrounds the preset region, and the conductive protection structure is made of an anti-dry-etching material; an insulation layer covering the first conductive pattern; and a second conductive pattern located on a side of the insulation layer away from the first conductive pattern, where the second conductive pattern is electrically connected to the first conductive pattern through the via-hole.
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公开(公告)号：US20210167097A1
公开(公告)日：2021-06-03
申请号：US16066162
申请日：2017-12-18
IPC: H01L27/12
Abstract: The present disclosure provides in some embodiments an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, an insulating layer, a via hole and a first blockage pattern; wherein the insulating layer is arranged on the base substrate, the via hole runs through the insulating layer; and an orthographic projection of the first blockage pattern on the base substrate partially or entirely covers an orthographic projection of the via hole on the base substrate.
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114.发明申请公开(公告)号：US20210036089A1
公开(公告)日：2021-02-04
申请号：US16910766
申请日：2020-06-24
Inventor： Guangyao LI , Dongfang WANG , Jun WANG , Haitao WANG , Qinghe WANG , Ning LIU , Wei LI , Yingbin HU , Yang ZHANG
Abstract: The present disclosure provides an OLED display panel and a method for detecting the OLED display panel, and a display device. The OLED display panel includes a base substrate including a display area and a non-display area surrounding the display area and having a first region adjacent to the display area. The display area includes a drive signal line and a power supply voltage signal line both extending from the display area to the first region. The drive signal line includes, in the first region, a first section of wiring at an anode layer, the power supply voltage signal line includes, in the first region, a second section of wiring at a gate metal layer, and parts of the drive signal line and the power supply voltage signal line in the display area are located at a source-drain metal layer.
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115.发明申请公开(公告)号：US20200369928A1
公开(公告)日：2020-11-26
申请号：US16768033
申请日：2019-11-07
Inventor： Ming LI , Kaimin WANG , Jie XIANG , Wei LI , Li WANG , Jing WANG , Zhiyong YANG , Fei CHAN , Fei LI , Shuzhen YANG
Abstract: An adhesive film includes an adhesive film body, and a plurality of deformable particles dispersed in the adhesive film body. A volume of each of the plurality of deformable particles is capable of shrinking under a trigger condition.
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Patent Agency Ranking
公开(公告)号：US20200266214A1
公开(公告)日：2020-08-20
申请号：US16349367
申请日：2018-09-14
Inventor： Dexiong SONG , Zhiyong YANG , Liwei HUANG , Shihua HUANG , Xue JIANG , Shibing YUAN , Fei CHEN , Wei LI , Chao FU , Na ZHANG , Yu DU , Xuemei DENG
IPC: H01L27/12
Abstract: The present disclosure provides a display panel, a method for manufacturing the same, and a display device. The insulation layer is provided above the first conductive electrodes in the bonding area of the display panel, the insulation layer covers the first conductive electrodes, and the insulation layer is capable of being pierced by ACF particles. When the display panel is bound to an FPC by an ACF, second conductive electrodes on the FPC can be electrically coupled to the first conductive electrodes on the display panel through the ACF particles, thereby achieving the bonding connection between the display panel and the FPC, even if a conductive foreign object falls into the area where the first conductive electrodes are located, short circuit cannot be caused, thereby improving the product yield.
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117.发明申请公开(公告)号：US20200243619A1
公开(公告)日：2020-07-30
申请号：US16345937
申请日：2019-01-07
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Dini XIE , Wei LI , Xiaojin ZHANG
Abstract: The present disclosure provides a display panel and a method for manufacturing the same, a detection method and a display device, and relates to the field of display technology. The display panel includes one or more detection units located on a substrate, wherein at least one of the one or more detection units comprises: a first electrode layer and a second electrode layer opposite to the first electrode layer; a light emitting layer located between the first electrode layer and the second electrode layer; and a fluorescent probe layer located between the first electrode layer and the light emitting layer.
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公开(公告)号：US20200171426A1
公开(公告)日：2020-06-04
申请号：US16611417
申请日：2019-01-22
Inventor： Guangyao LI , Guangcai YUAN , Dongfang WANG , Jun WANG , Qinghe WANG , Wei LI , Leilei CHENG
Abstract: The present disclosure provides a gas screening film including at least one gas screening element, each of the at least one gas screening element includes a transistor including a gate, an insulation spacing layer, a first electrode, a semiconductor nanosheet separation layer and a second electrode, and the insulation spacing layer is disposed between the gate and the semiconductor nanosheet separation layer. The present disclosure further provides a manufacturing method of the gas screening film and a face mask. The gas screening film can screen and separate various different gases as necessary.
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119.发明申请公开(公告)号：US20200161196A1
公开(公告)日：2020-05-21
申请号：US16452952
申请日：2019-06-26
Inventor： Yingbin HU , Ce ZHAO , Yuankui DING , Wei SONG , Jun WANG , Yang ZHANG , Wei LI , Liangchen YAN
IPC: H01L21/66 , H01L29/66 , H01L21/44 , H01L21/467 , G03F7/20
Abstract: The present disclosure provides a method for determining a width-to-length ratio of a channel region of a thin film transistor (TFT). The method includes: S1, setting an initial width-to-length ratio of the channel region; S2, manufacturing a TFT by using a mask plate according to the initial width-to-length ratio; S3, testing the TFT manufactured according to the initial width-to-length ratio; S4, determining whether or not the test result satisfies a predetermined condition, performing S5 if the test result satisfies the predetermined condition, and performing S6 if the test result does not satisfy the predetermined condition; S5, determining the initial width-to-length ratio as the width-to-length ratio of the channel region of the TFT; S6, changing the value of the initial width-to-length ratio, adjusting a position of the mask plate according to the changed initial width-to-length ratio, and performing S2 to S4 again.
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公开(公告)号：US20200052053A1
公开(公告)日：2020-02-13
申请号：US16536942
申请日：2019-08-09
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zhen SONG , Guoying WANG , Wei LI
Abstract: The present disclosure provides a display substrate, a fabricating method thereof, and a display device. The display substrate includes a substrate; at least one pixel on a side of the substrate, the at least one pixel comprising a driving transistor, the driving transistor comprising a drain; an insulating layer on a side of the driving transistor away from the substrate, the insulating layer covering the driving transistor and having a first via hole opposite to the drain; an auxiliary conductive structure on a side of the insulating layer away from the substrate, and the auxiliary conductive structure connected to the drain through the first via hole; and a first planarization layer on a side of the auxiliary conductive structure away from the substrate, and having a second via hole disposed therein.
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