公开(公告)号：US20230092320A1

公开(公告)日：2023-03-23

申请号：US18059165

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kunal R. Parekh ,  Aaron S. Yip

IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11582

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230080749A1

公开(公告)日：2023-03-16

申请号：US18051459

申请日：2022-10-31

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L49/02

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

公开(公告)号：US20230057745A1

公开(公告)日：2023-02-23

申请号：US18045417

申请日：2022-10-10

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kunal R. Parekh

IPC: H01L27/11582 ,  H01L29/47 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L21/285

Abstract: A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

公开(公告)号：US20230051863A1

公开(公告)日：2023-02-16

申请号：US17712935

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C11/4091 ,  G11C11/408

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

公开(公告)号：US20230048855A1

公开(公告)日：2023-02-16

申请号：US17884365

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Aliasger T. Zaidy ,  Glen E. Hush ,  Kunal R. Parekh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

公开(公告)号：US20220336273A1

公开(公告)日：2022-10-20

申请号：US17850848

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/306 ,  H01L21/311

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

公开(公告)号：US11348933B2

公开(公告)日：2022-05-31

申请号：US17125639

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Justin B. Dorhout ,  Nancy M. Lomeli

IPC: H01L21/768 ,  H01L23/528 ,  H01L27/115 ,  H01L29/788 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524

Abstract: Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

公开(公告)号：US11271002B2

公开(公告)日：2022-03-08

申请号：US16382932

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US20210398945A1

公开(公告)日：2021-12-23

申请号：US16905747

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L49/02

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

公开(公告)号：US20210398897A1

公开(公告)日：2021-12-23

申请号：US16905698

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11524 ,  G11C7/18 ,  H01L25/18 ,  H01L23/00 ,  H01L23/528

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure to are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.