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公开(公告)号：US20220149068A1
公开(公告)日：2022-05-12
申请号：US17092916
申请日：2020-11-09
发明人： Yifen Liu , Yan Song , Albert Fayrushin , Naiming Liu , Yingda Dong , George Matamis
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L23/522
摘要： An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
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公开(公告)号：US11302634B2
公开(公告)日：2022-04-12
申请号：US16790148
申请日：2020-02-13
发明人： Lifang Xu , Jian Li , Graham R. Wolstenholme , Paolo Tessariol , George Matamis , Nancy M. Lomeli
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768 , H01L27/11582 , H01L27/11556
摘要： Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
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公开(公告)号：US20240188299A1
公开(公告)日：2024-06-06
申请号：US18525362
申请日：2023-11-30
发明人： Christopher J. Larsen , S M Istiaque Hossain , David A. Daycock , Kevin R. Gast , George Matamis , Lingyu Kong , Sok Han Wong , Lhaang Chee Ooi , Wenjie Li
CPC分类号： H10B43/27 , G11C16/0483 , H10B43/10 , H10B43/35
摘要： Methods, systems, and devices for three-dimensional memory array formation techniques are described. A memory device may include a stack of materials over a substrate. The memory device may include an array of first pillars and an array of second pillars extending at least partially through the stack of materials. One or more first pillars may be excluded from one or more columns of pillars of the array first pillars. The memory device may include dielectric material in a slit extending at least partially through the stack of materials. Based on the exclusion of the one or more first pillars, the slit may have a greater width at a first portion through the stack of materials than a second portion through the stack of materials. The dielectric material located in the slit may also have a greater width at the first portion than at the second portion.
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公开(公告)号：US11956954B2
公开(公告)日：2024-04-09
申请号：US17092916
申请日：2020-11-09
发明人： Yifen Liu , Yan Song , Albert Fayrushin , Naiming Liu , Yingda Dong , George Matamis
IPC分类号： H10B43/27 , H01L23/522 , H10B43/10 , H10B43/35 , H10B43/40
CPC分类号： H10B43/27 , H01L23/5226 , H10B43/10 , H10B43/35 , H10B43/40
摘要： An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
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公开(公告)号：US11488677B2
公开(公告)日：2022-11-01
申请号：US17247435
申请日：2020-12-10
摘要： A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.
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公开(公告)号：US20220230960A1
公开(公告)日：2022-07-21
申请号：US17658404
申请日：2022-04-07
发明人： Lifang Xu , Jian Li , Graham R. Wolstenholme , Paolo Tessariol , George Matamis , Nancy M. Lomeli
IPC分类号： H01L23/528 , H01L23/522 , H01L21/768
摘要： Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
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公开(公告)号：US11271002B2
公开(公告)日：2022-03-08
申请号：US16382932
申请日：2019-04-12
发明人： M. Jared Barclay , Merri L. Carlson , Saurabh Keshav , George Matamis , Young Joon Moon , Kunal R. Parekh , Paolo Tessariol , Vinayak Shamanna
IPC分类号： H01L27/11556 , H01L27/11519 , H01L21/311 , H01L27/11582 , H01L27/11565
摘要： A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.
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8.发明公开公开(公告)号：US20240244845A1
公开(公告)日：2024-07-18
申请号：US18622671
申请日：2024-03-29
发明人： Yifen Liu , Yan Song , Albert Fayrushin , Naiming Liu , Yingda Dong , George Matamis
IPC分类号： H10B43/27 , H01L23/522 , H10B43/10 , H10B43/35 , H10B43/40
CPC分类号： H10B43/27 , H01L23/5226 , H10B43/10 , H10B43/35 , H10B43/40
摘要： An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
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公开(公告)号：US20230022858A1
公开(公告)日：2023-01-26
申请号：US17960252
申请日：2022-10-05
摘要： A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.
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公开(公告)号：US20220367512A1
公开(公告)日：2022-11-17
申请号：US17869732
申请日：2022-07-20
发明人： S.M. Istiaque Hossain , Prakash Rau Mokhna Rau , Arun Kumar Dhayalan , Damir Fazil , Joel D. Peterson , Anilkumar Chandolu , Albert Fayrushin , George Matamis , Christopher Larsen , Rokibul Islam
IPC分类号： H01L27/11582 , G11C5/02 , H01L21/768 , G11C16/04 , G11C5/06
摘要： Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
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