公开(公告)号：US20250006251A1

公开(公告)日：2025-01-02

申请号：US18829647

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Glen E. Hush ,  Sean S. Eilert ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

公开(公告)号：US20230051863A1

公开(公告)日：2023-02-16

申请号：US17712935

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C11/4091 ,  G11C11/408

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

公开(公告)号：US20230048855A1

公开(公告)日：2023-02-16

申请号：US17884365

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Aliasger T. Zaidy ,  Glen E. Hush ,  Kunal R. Parekh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

公开(公告)号：US12112793B2

公开(公告)日：2024-10-08

申请号：US17885374

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Glen E. Hush ,  Sean S. Eilert ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F3/0656 ,  G06F13/1673 ,  G06F13/28 ,  G11C7/08 ,  G11C7/1039 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/78 ,  H01L22/12 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  G06F2213/28 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/1601 ,  H01L2224/16221 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1436

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

公开(公告)号：US20230051235A1

公开(公告)日：2023-02-16

申请号：US17885291

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy

IPC: H01L21/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.

公开(公告)号：US20230046050A1

公开(公告)日：2023-02-16

申请号：US17830981

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Glen E. Hush ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C7/10 ,  G11C7/08 ,  H01L23/00 ,  H01L25/065

Abstract: A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

公开(公告)号：US20250104761A1

公开(公告)日：2025-03-27

申请号：US18971871

申请日：2024-12-06

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Glen E. Hush ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

公开(公告)号：US12165696B2

公开(公告)日：2024-12-10

申请号：US17830981

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Glen E. Hush ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

公开(公告)号：US11915742B2

公开(公告)日：2024-02-27

申请号：US17885242

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kunal R. Parekh ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: G06F13/00 ,  G11C11/4093 ,  G06F13/16 ,  G06F3/06 ,  G11C11/4096 ,  H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/66 ,  H01L25/18 ,  H01L25/00 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G16B50/10 ,  G16B30/00 ,  G06F13/28

CPC classification number: G11C11/4093 ,  G06F3/0656 ,  G06F13/1673 ,  G06F13/28 ,  G11C7/08 ,  G11C7/1039 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/78 ,  H01L22/12 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  G06F2213/28 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/1601 ,  H01L2224/16221 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/14335

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of a genetic sequence from the memory die and through a wafer-on-wafer bond. The logic die can also perform a genome annotation lotic operation to attach biological information to the genetic sequence. An annotated genetic sequence can be provided as an output.

公开(公告)号：US12112792B2

公开(公告)日：2024-10-08

申请号：US17712935

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: H01L23/00 ,  G06F3/06 ,  G06F13/16 ,  G06F13/28 ,  G11C7/08 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/66 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F3/0656 ,  G06F13/1673 ,  G06F13/28 ,  G11C7/08 ,  G11C7/1039 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G16B30/00 ,  G16B50/10 ,  H01L21/78 ,  H01L22/12 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  G06F2213/28 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/1601 ,  H01L2224/16221 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2924/1436

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.