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公开(公告)号：US12034940B2
公开(公告)日：2024-07-09
申请号：US17539348
申请日：2021-12-01
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N19/176 , H04N19/105 , H04N19/52 , H04N19/70
CPC classification number: H04N19/176 , H04N19/105 , H04N19/52 , H04N19/70
Abstract: An encoder, includes: circuitry; and memory. Using the memory, the circuitry: in inter prediction for a current block, determines a base motion vector, and writes, in an encoded signal, a delta motion vector representing (i) one direction among a plurality of directions including a diagonal direction and (ii) a distance from the base motion vector; and encodes the current block using the delta motion vector and the base motion vector as a motion vector of the current block.
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公开(公告)号：US12034938B2
公开(公告)日：2024-07-09
申请号：US18171242
申请日：2023-02-17
Inventor： Jing Ya Li , Chong Soon Lim , Han Boon Teo , Hai Wei Sun , Che Wei Kuo , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Yusuke Kato
IPC: G06V10/00 , H04N19/126 , H04N19/156 , H04N19/159 , H04N19/18 , H04N19/52 , H04N19/61
CPC classification number: H04N19/159 , H04N19/126 , H04N19/156 , H04N19/18 , H04N19/52 , H04N19/61
Abstract: An image encoder is provided including circuitry and a memory coupled to the circuitry. The circuitry, in operation, responds to a size of a block satisfying a size condition by generating a prediction image using a prediction mode selected from a plurality of prediction modes. The plurality of prediction modes include a first prediction mode in which a prediction process uses a motion vector and a reference block in a same picture as the block. The circuitry encodes the block using the prediction image.
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公开(公告)号：US20240223766A1
公开(公告)日：2024-07-04
申请号：US18606178
申请日：2024-03-15
Inventor： Han Boon Teo , Chong Soon Lim , Jingying Gao , Praveen Kumar Yadav , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/132 , H04N19/172 , H04N19/186 , H04N19/30 , H04N19/503 , H04N19/593 , H04N19/70
CPC classification number: H04N19/132 , H04N19/172 , H04N19/186 , H04N19/30 , H04N19/503 , H04N19/593 , H04N19/70
Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry performs a first resampling process that changes a resolution of an image to be processed corresponding to one of an image to be encoded or a reference image for the image to be encoded, and in the first resampling process, the circuitry changes the resolution of the image to be processed, by changing a resolution of one component among a plurality of components of the image to be processed, and retains each resolution of one or more remaining components among the plurality of components.
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公开(公告)号：US12028554B2
公开(公告)日：2024-07-02
申请号：US18052108
申请日：2022-11-02
Inventor： Chu Tong Wang , Chong Soon Lim , Han Boon Teo , Hai Wei Sun , Jing Ya Li , Che-Wei Kuo , Tadamasa Toma , Takahiro Nishi , Kiyofumi Abe , Yusuke Kato
IPC: H04N19/82 , H04N19/117 , H04N19/132 , H04N19/167 , H04N19/17 , H04N19/186
CPC classification number: H04N19/82 , H04N19/117 , H04N19/132 , H04N19/167 , H04N19/17 , H04N19/186
Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in response to a first reconstructed image sample being located outside a virtual boundary, duplicates a reconstructed sample located inside and adjacent to the virtual boundary to generate the first reconstructed image sample. The circuitry generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to the first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.
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公开(公告)号：US20240179341A1
公开(公告)日：2024-05-30
申请号：US18433707
申请日：2024-02-06
Inventor： Chong Soon LIM , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Ru Ling Liao , Jing Ya Li , Tadamasa Toma , Takahiro Nishi , Kiyofumi Abe , Ryuichi Kanoh
IPC: H04N19/52
CPC classification number: H04N19/52
Abstract: An encoder which includes circuitry and memory. Using the memory, the circuitry generates a list which includes candidates for a first motion vector for a first partition. The list has a maximum list size and an order of the candidates, and at least one of the maximum list size or the order of the candidates is dependent on at least one of a partition size or a partition shape of the first partition. The circuitry selects the first motion vector from the candidates included in the list; encodes an index indicating the first motion vector among the candidates in the list into the bitstream based on the maximum list size; and generates the predicted image for the first partition using the first motion vector.
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Patent Agency Ranking
公开(公告)号：US11985349B2
公开(公告)日：2024-05-14
申请号：US17373066
申请日：2021-07-12
Inventor： Chong Soon Lim , Han Boon Teo , Takahiro Nishi , Tadamasa Toma , Ru Ling Liao , Sughosh Pavan Shashidhar , Hai Wei Sun
IPC: H04N19/597 , G06T5/00 , H04N5/00 , H04N19/159 , H04N19/176 , H04N19/46 , H04N19/85
CPC classification number: H04N19/597 , G06T5/006 , H04N19/159 , H04N19/176 , H04N19/46 , H04N19/85
Abstract: An encoder capable of properly handling an image to be encoded or decoded includes processing circuitry and memory connected to the processing circuitry. Using the memory, the processing circuitry: obtains parameters including at least one of (i) one or more parameters related to a first process for correcting distortion in an image captured with a wide angle lens and (ii) one or more parameters related to a second process for stitching a plurality of images; generates an encoded image by encoding a current image to be processed that is based on the image or the plurality of images; and writes the parameters into a bitstream including the encoded image.
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公开(公告)号：US20240121384A1
公开(公告)日：2024-04-11
申请号：US18539753
申请日：2023-12-14
Inventor： Jing Ya LI , Ru Ling Liao , Chong Soon Lim , Han Boon Teo , Hai Wei Sun , Che Wei Kuo , Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma
IPC: H04N19/105 , H04N19/136 , H04N19/159 , H04N19/176 , H04N19/52 , H04N19/80
CPC classification number: H04N19/105 , H04N19/136 , H04N19/159 , H04N19/176 , H04N19/52 , H04N19/80
Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of horizontal gradient values; derives, as a first parameter, the total sum of the absolute values of horizontal gradient values; derives, as a second parameter, the total sum of the absolute values of vertical gradient values; derives a horizontal-related pixel difference value; derives, as a third parameter, the total sum of the absolute values of horizontal-related pixel difference values; derives a vertical-related pixel difference value; derives, as a fourth parameter, the total sum of the absolute values of vertical-related pixel difference values; and generates a prediction image using the first to fourth parameters.
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公开(公告)号：US11949884B2
公开(公告)日：2024-04-02
申请号：US18118238
申请日：2023-03-07
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N19/159 , H04N19/119 , H04N19/139 , H04N19/513
CPC classification number: H04N19/159 , H04N19/119 , H04N19/139 , H04N19/521
Abstract: An encoder encodes a video, and includes: circuitry; and memory coupled to the circuitry. Using the memory, the circuitry: obtains at least two items of prediction information for a first partition included in the video; derives at least one template from neighboring samples which neighbor the first partition; calculates at least two costs, using the at least one template and the at least two items of prediction information; using the at least two costs, (i) determines at least one splitting direction for the first partition or (ii) assigns one of the at least two items of prediction information to a second partition split from the first partition according to the splitting direction, and another thereof to a third partition split from the first partition according to the splitting direction; and encodes the first partition according to the splitting direction and the at least two items of prediction information.
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公开(公告)号：US11924456B2
公开(公告)日：2024-03-05
申请号：US18066873
申请日：2022-12-15
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N19/51 , H04N19/176 , H04N19/182
CPC classification number: H04N19/51 , H04N19/176 , H04N19/182
Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.
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公开(公告)号：US11889104B2
公开(公告)日：2024-01-30
申请号：US18056542
申请日：2022-11-17
Inventor： Kiyofumi Abe , Takahiro Nishi , Tadamasa Toma , Ryuichi Kanoh , Chong Soon Lim , Ru Ling Liao , Hai Wei Sun , Sughosh Pavan Shashidhar , Han Boon Teo , Jing Ya Li
IPC: H04N11/02 , H04N19/52 , H04N19/119 , H04N19/176
CPC classification number: H04N19/52 , H04N19/119 , H04N19/176
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.
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