公开(公告)号：US20070270017A1

公开(公告)日：2007-11-22

申请号：US11419609

申请日：2006-05-22

Applicant: Robert Hardacker ,  Robert Unger

Inventor： Robert Hardacker ,  Robert Unger

IPC: H01R13/627

CPC classification number: H01P1/042

Abstract: To achieve ultra-high bandwidth data transmission according to embodiments of the invention, a plurality of parallel 60 GHz band frequency signals traveling in substantially parallel paths is employed. A connector or housing includes a plurality of metallized, grounded shells or chambers having antenna pairs that are embedded therein. There is no physical contact between the transmitter and receiver antennas. Instead, the metallized, grounded connector chambers provide isolation between adjacent radio links which all operate on the same frequency.

Abstract translation: 为了实现根据本发明的实施例的超高带宽数据传输，采用基本上平行路径行进的多个平行的60GHz频带频率信号。 连接器或壳体包括多个金属化，接地的壳或具有嵌入其中的天线对的室。 发射机和接收机天线之间没有物理接触。 相反，金属化的接地连接器室提供了在相同频率上工作的相邻无线电链路之间的隔离。

公开(公告)号：US20070118864A1

公开(公告)日：2007-05-24

申请号：US11649086

申请日：2007-01-03

Applicant: Mark Champion ,  Robert Unger ,  Robert Hardacker

Inventor： Mark Champion ,  Robert Unger ,  Robert Hardacker

IPC: H04N7/18 ,  H04N7/173 ,  H04N7/16

CPC classification number: G09G5/006 ,  G09G2370/045 ,  G09G2370/047 ,  G09G2370/10 ,  G09G2370/12 ,  G09G2370/16 ,  H04L12/2805 ,  H04L29/06027 ,  H04L67/12 ,  H04N21/43635 ,  H04N21/43637

Abstract: A transmit digital processing system for wireless transmission of HDMI and/or DVI data using an FPGA. The FPGA converts the data into two data streams and includes a front end component multiplexing video data with control data. A complementary receive FPGA is also disclosed.

公开(公告)号：US20070094489A1

公开(公告)日：2007-04-26

申请号：US11256315

申请日：2005-10-21

Applicant: Takaaki Ota ,  Dipendu Saha ,  Robert Hardacker

Inventor： Takaaki Ota ,  Dipendu Saha ,  Robert Hardacker

IPC: G06F15/177

CPC classification number: G06F9/4401

Abstract: The present embodiments provide apparatuses, systems and methods for that allow the booting of an embedded system from an off-board memory. In some embodiments, a system is provided that includes a circuit board comprising a processor, a memory, an operating system stored in the memory and utilized to at least in part control processor operation, and an external memory access comprising a first port onboard the circuit board, a local off-board memory, wherein the local off-board memory is coupled to the first port, and a root file system stored in the local off-board memory used while booting the operating system.

Abstract translation: 本实施例提供了允许从板外存储器引导嵌入式系统的装置，系统和方法。 在一些实施例中，提供了一种系统，其包括电路板，该电路板包括处理器，存储器，存储在存储器中并用于至少部分地控制处理器操作的操作系统，以及包括电路板上的第一端口的外部存储器访问 板，本地板外存储器，其中本地板外存储器耦合到第一端口，以及存储在引导操作系统时使用的本地板外存储器中的根文件系统。

公开(公告)号：US20060160489A1

公开(公告)日：2006-07-20

申请号：US11035845

申请日：2005-01-14

Applicant: Robert Hardacker

Inventor： Robert Hardacker

IPC: H04B7/00

CPC classification number: H04B7/0808 ,  H04B7/0814

Abstract: In a wireless 60GHz data communication system, one or both of the source and receiver can have multiple antennae, with the antenna providing the best signal strength being dynamically selected. In this way, if a person or other object momentarily crosses between the source and receiver, blocking data communication from one antenna, the other antenna can be used.

Abstract translation: 在无线60GHz数据通信系统中，源和接收机中的一个或两个可以具有多个天线，天线提供最佳信号强度被动态选择。 以这种方式，如果人或其他物体在源和接收器之间短暂地交叉，则阻止来自一个天线的数据通信，则可以使用另一个天线。

公开(公告)号：US20060092893A1

公开(公告)日：2006-05-04

申请号：US11215463

申请日：2005-08-30

Applicant: Mark Champion ,  Robert Unger ,  Robert Hardacker

Inventor： Mark Champion ,  Robert Unger ,  Robert Hardacker

IPC: H04Q7/24 ,  H04J3/22 ,  H04J3/16

CPC classification number: G09G5/006 ,  G09G2370/045 ,  G09G2370/047 ,  G09G2370/10 ,  G09G2370/12 ,  G09G2370/16 ,  H04L12/2805 ,  H04L29/06027 ,  H04L67/12 ,  H04N21/43635 ,  H04N21/43637

Abstract: A transmit digital processing system for wireless transmission of HDMI and/or DVI data using an FPGA. The FPGA converts the data into two data streams and includes a front end component multiplexing video data with control data. A complementary receive FPGA is also disclosed.

公开(公告)号：US20050135611A1

公开(公告)日：2005-06-23

申请号：US11036932

申请日：2005-01-14

Applicant: Robert Hardacker

Inventor： Robert Hardacker

IPC: H04K1/00

CPC classification number: H04L63/0428 ,  H04L63/061 ,  H04L63/18 ,  H04W12/0013

Abstract: Data such as high definition (HD) video may be sent from a transmitter such as a laptop computer to a receiver such as a video projector using a 60 GHz (and, hence, inherently directional, short range, and thus secure) forward channel wireless link. Encryption information such as encryption keys are also exchanged over the forward channel link. The encryption information is used to encrypt control signals that can be exchanged over a reverse channel link that may operate at a frequency of 2.4 GHz.

Abstract translation: 诸如高清晰度（HD）视频的数据可以从诸如膝上型计算机的发射机发送到诸如使用60GHz（并且因此固有的定向，短距离，因此是安全的）正向信道无线电的视频投影仪的接收机 链接。 诸如加密密钥的加密信息也通过前向信道链路交换。 加密信息用于加密可以通过可在2.4GHz频率下操作的反向信道链路交换的控制信号。

公开(公告)号：US20050105498A1

公开(公告)日：2005-05-19

申请号：US10790162

申请日：2004-03-01

Applicant: Robert Hardacker ,  David Desch

Inventor： Robert Hardacker ,  David Desch

IPC: G09G5/00 ,  H04L12/28 ,  H04L29/06 ,  H04W88/02 ,  H04L12/66

CPC classification number: G09G5/006 ,  H04L29/06027 ,  H04L65/607 ,  H04N21/2381 ,  H04N21/4363 ,  H04N21/4381 ,  H04W88/02

Abstract: Digital Visual Interface (DVI), or High Definition Multi-media Interface (HDMI), data is received from a source and sent to a transmitter chip that includes a transition minimized differential signaling (TMDS) receiver that outputs a 3-data and 1-clock physical signaling stream representing the DVI or HDMI data. This stream is rendered into I and Q data by an ASIC or FPGA and sent to a wireless transmitter for modulation, upconverting, and transmission to, e.g., a nearby display device without ever rendering the data into baseband video on the transmitter chip. The display device has a receiver chip that is essentially the inverse of the transmitter chip.

Abstract translation: 数字视频接口（DVI）或高清多媒体接口（HDMI），数据从源接收并发送到发射机芯片，发射机芯片包括转换最小化差分信号（TMDS）接收机，其输出3数据和1- 表示DVI或HDMI数据的时钟物理信令流。 该流由ASIC或FPGA呈现为I和Q数据，并发送到无线发射机进行调制，上变频和传输到例如附近的显示设备，而不会将数据呈现在发射机芯片上的基带视频中。 显示装置具有基本上与发射机芯片相反的接收器芯片。