公开(公告)号：US06199140B1

公开(公告)日：2001-03-06

申请号：US08967314

申请日：1997-10-30

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G06F1200

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A content addressable memory (CAM) device. The CAM device is a synchronous device that may perform all of the following operations all in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction from an instruction bus instructing the CAM device to compare the comparand data with a first group of CAM cells in a CAM array; (3) perform the comparison of the comparand data with the first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells. The status information may include a match flag, multiple match flag, full flag, skip bit, empty bit, or a device identification for the CAM device.

Abstract translation: 内容可寻址存储器（CAM）设备。 CAM设备是同步设备，其可以在一个时钟周期内执行所有以下操作：（1）从比较总线接收比较数据; （2）从指令总线接收指令，指示CAM设备将比较数据与CAM阵列中的第一组CAM单元进行比较; （3）比较数据与第一组CAM单元进行比较; （4）生成CAM阵列中存储与比较数据匹配的数据的位置的匹配地址; （5）访问存储在CAM阵列中的CAM单元的第二组中的数据，其中第二组CAM单元可以存储与匹配位置相关联的数据; 和（6）向输出总线输出匹配地址，存储在第二组CAM单元中的数据和/或与匹配地址或第二组CAM单元相对应的状态信息。 状态信息可以包括用于CAM设备的匹配标志，多重匹配标志，满标志，跳过位，空位或设备标识。

公开(公告)号：US08982596B1

公开(公告)日：2015-03-17

申请号：US13301499

申请日：2011-11-21

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00 ,  G11C15/04 ,  G11C29/24 ,  G11C29/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C29/24 ,  G11C29/70 ,  G11C29/816 ,  G11C29/848

Abstract: A CAM device includes a CAM array that can implement column redundancy in which a defective column segment in a selected block can be functionally replaced by a selected column segment of the same block, and/or by a spare column segment of the same block.

Abstract translation: CAM设备包括可以实现列冗余的CAM阵列，其中所选块中的缺陷列段可以由相同块的所选列段和/或由同一块的备用列段功能地替换。

公开(公告)号：US08730704B1

公开(公告)日：2014-05-20

申请号：US13371236

申请日：2012-02-10

Applicant: Bindiganavale S. Nataraj ,  John Zimmer ,  Sandeep Khanna ,  Vinay Iyengar ,  Chetan Deshpande

Inventor： Bindiganavale S. Nataraj ,  John Zimmer ,  Sandeep Khanna ,  Vinay Iyengar ,  Chetan Deshpande

IPC: G11C15/00

CPC classification number: G11C15/04 ,  H01L27/1052

Abstract: A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-1 layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-1 layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-2 layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-1 layer to the metal-2 layer.

Abstract translation: 公开了一种CAM器件，其包括CAM单元阵列，其中使用介于CAM器件的多晶硅层和CAM器件的金属层之间的导电层将CAM单元组的比较电路连接在一起。 这允许CAM阵列的数据线（例如，位线和/或比较线）形成在CAM器件的金属1层中，这继而允许CAM阵列的匹配线形成在 CAM设备的金属层2层。 可以是硅化物层的导电层通过从导电层穿过金属-1层延伸到金属层2的通孔连接到匹配线。

公开(公告)号：US20130009619A1

公开(公告)日：2013-01-10

申请号：US13618652

申请日：2012-09-14

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: G05F1/10

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US08274265B1

公开(公告)日：2012-09-25

申请号：US12028774

申请日：2008-02-08

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  De Cai Li ,  Chetan Deshpande

IPC: G05F1/59 ,  G05F1/618

CPC classification number: H02M3/1584 ,  H02M2003/1586 ,  Y10T307/582

Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract translation: 用于向负载递送电力的集成电路装置包括控制器电路，级联电路和电力输送电路。 控制器电路产生多个控制信号。 级联电路从控制器电路接收控制信号，并将控制信号依次输出到级联总线上。 功率传递电路响应于控制信号之一，接收来自控制器电路的控制信号并将一定量的电流传送到负载。

公开(公告)号：US07920397B1

公开(公告)日：2011-04-05

申请号：US12771657

申请日：2010-04-30

Applicant: Bindiganavale S. Nataraj ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Bindiganavale S. Nataraj ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C7/12 ,  G11C11/419 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/1204

Abstract: A memory device operates in a calibration mode during which the effects of bit line leakage current are measured and to operate in a normal mode during which the bit line current is adjusted to compensate for leakage according to the results of the calibration mode. In the calibration mode, a leakage-free sense operation is performed to determine the differential voltage generated on the bit lines in response to a data value. Then, a leakage-susceptible test read operation is performed to determine the differential voltage generated on the bit lines in response to the data value. A detection circuit measures the difference between the differential voltages generated in the leakage-free and leakage-susceptible test read operations to generate a compensation signal, which subsequently adjusts the bit line compensation current during the normal mode.

Abstract translation: 存储器件在校准模式下工作，在该校准模式期间测量位线泄漏电流的影响并且在正常模式下操作，在正常模式期间，根据校准模式的结果调整位线电流以补偿泄漏。 在校准模式中，执行无泄漏检测操作以确定响应于数据值在位线上产生的差分电压。 然后，执行泄漏敏感的测试读取操作，以响应于数据值来确定在位线上产生的差分电压。 检测电路测量在无泄漏和易泄漏的测试读取操作中产生的差分电压之间的差异，以产生补偿信号，随后在正常模式期间调整位线补偿电流。

公开(公告)号：US07876590B2

公开(公告)日：2011-01-25

申请号：US12873183

申请日：2010-08-31

Applicant: Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract translation: 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

公开(公告)号：US07826242B2

公开(公告)日：2010-11-02

申请号：US12619607

申请日：2009-11-16

Applicant: Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Sachin Joshi ,  Mark Birman ,  Maheshwaran Srinivasan ,  Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enable input. Each sequencing logic circuit includes an input and an output, and is configured to count sequences of match signals from the CAM rows. The programmable interconnect structure selectively connects the match line of any CAM row to the input of any sequencing logic circuit, and selectively connects the output of any sequencing logic circuit to the enable input of any CAM row.

Abstract translation: 内容可寻址存储器（CAM）设备包括多个CAM行，多个排序逻辑电路和可编程互连结构。 每个CAM行包括多个CAM单元，以在匹配线上生成匹配信号并且包括使能输入。 每个排序逻辑电路包括输入和输出，并且被配置为对来自CAM行的匹配信号的序列进行计数。 可编程互连结构选择性地将任何CAM行的匹配线连接到任何排序逻辑电路的输入，并且将任何排序逻辑电路的输出选择性地连接到任何CAM行的使能输入。

公开(公告)号：US07821844B2

公开(公告)日：2010-10-26

申请号：US12617369

申请日：2009-11-12

Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates match results for the row. The programmable interconnect structure coupled to each CAM row, and is configured to logically connect any number N of selected CAM rows together to form a data word chain spanning N rows, regardless of whether the selected CAM rows are contiguous.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行和多个CAM行，每行包括用于存储数据字并耦合到指示行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为将任何数目N个所选择的CAM行逻辑地连接在一起，以形成横跨N行的数据字链，而不管所选择的CAM行是否是连续的。

公开(公告)号：US07707203B2

公开(公告)日：2010-04-27

申请号：US11173656

申请日：2005-06-30

Applicant: Adam Hyder ,  Sandeep Khanna ,  Joseph Ting

Inventor： Adam Hyder ,  Sandeep Khanna ,  Joseph Ting

IPC: G06F7/00 ,  G06F17/00

CPC classification number: G06F17/30873 ,  G06Q10/10 ,  G06Q10/1053 ,  Y10S707/947

Abstract: A computer system and method for capture, managing and presenting data obtained from various often unrelated postings via the Internet for examination by a user. This system includes a scraping module having one or more scraping engines operable to scrape information data sets from listings on the corporate sites and web sites, direct feeds, and other sources, wherein the scraping module receives and stores the scraped listing information data sets in a database. The system also has a management platform coordinating all operation of and communication between the sources, system administrators and processing modules. The processing modules in the platform include scraping management module analyzing selected scraped data stored in the database, and a categorization module that examines and categorizes each data set stored in the database into one or more of a predetermined set of categories and returns categorized data sets to the database.

Abstract translation: 一种计算机系统和方法，用于捕获，管理和呈现通过互联网从各种经常不相关的过帐获得的数据，以供用户检查。 该系统包括具有一个或多个刮削引擎的刮削模块，其可操作以从公司站点和网站，直接馈送和其他源上的列表中刮取信息数据集，其中，刮削模块接收并将刮除的列表信息数据集存储在 数据库。 该系统还具有协调源，系统管理员和处理模块之间的所有操作和通信的管理平台。 平台中的处理模块包括分析存储在数据库中的所选择的刮取数据的刮擦管理模块，以及分类模块，其将存储在数据库中的每个数据集合分类为一组或多个预定类别，并将分类数据集返回到 数据库。