公开(公告)号：US10853923B2

公开(公告)日：2020-12-01

申请号：US15927820

申请日：2018-03-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram VijayanBabu Appia ,  Sujith Shivalingappa

IPC: G06T5/00 ,  G06T3/00

Abstract: A method for geometrically correcting a distorted input frame and generating an undistorted output frame includes capturing and storing an input frame in an external memory, allocating an output frame with an output frame size and dividing the output frame into output blocks, computing a size of the input blocks in the input image corresponding to each output blocks, checking if the size of the input blocks is less than the size of the internal memory and if not dividing until the required input block size of divided sub blocks is less than the size of the internal memory, programming an apparatus with input parameters, fetching the input blocks into an internal memory, processing each of the divided sub blocks sequentially and processing the next output block in step until all the output blocks are processed; and composing the output frame for each of the blocks in the output frame.

公开(公告)号：US10652582B2

公开(公告)日：2020-05-12

申请号：US15871713

申请日：2018-01-15

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

IPC: H04N19/80 ,  H04N19/423 ,  H04N19/86

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

公开(公告)号：US10455238B2

公开(公告)日：2019-10-22

申请号：US15853474

申请日：2017-12-22

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US20190235927A1

公开(公告)日：2019-08-01

申请号：US16377966

申请日：2019-04-08

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/52 ,  G06F9/48 ,  G06F11/07

CPC classification number: G06F9/5044 ,  G06F5/12 ,  G06F9/4881 ,  G06F9/4887 ,  G06F9/52 ,  G06F9/522 ,  G06F9/544 ,  G06F11/0757 ,  G06T1/20

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

公开(公告)号：US20190096041A1

公开(公告)日：2019-03-28

申请号：US15714862

申请日：2017-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody ,  Gang Hua ,  Brian Okchon Chae ,  Shashank Dabral ,  Hetul Sanghvi ,  Vikram VijayanBabu Appia ,  Sujith Shivalingappa

IPC: G06T5/00 ,  G06T3/00 ,  G06T5/40 ,  G06T3/40 ,  G06T7/11 ,  G06T5/20

Abstract: An apparatus and method for geometrically correcting a distorted input frame and generating an undistorted output frame. The apparatus includes an external memory block that stores the input frame, a counter block to compute output coordinates of the output frame for a region based on a block size of the region, a back mapping block to generate input coordinates corresponding to each of the output coordinates, a bounding module to compute input blocks corresponding to each of the input coordinates, a buffer module to fetch data corresponding to each of the input blocks, an interpolation module to interpolate data from the buffer module and a display module that receives the interpolated data for each of the regions and stitch an output image. The method includes determining the size of the output block based on a magnification data.

公开(公告)号：US20180184125A1

公开(公告)日：2018-06-28

申请号：US15871713

申请日：2018-01-15

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mullangi Venkata Ratna Reddy

IPC: H04N19/80 ,  H04N19/423 ,  H04N19/86

CPC classification number: H04N19/80 ,  H04N19/423 ,  H04N19/86

Abstract: A de-blocking filter includes a reconstructed memory that is configured to store reconstructed pixels corresponding to a current macroblock of a video image to be filtered. The current macroblock includes a set of sub-blocks, each sub-block having horizontal edges and vertical edges. An internal pixel buffer in the de-blocking filter is configured to store pixels corresponding to the set of sub-blocks from the reconstructed memory, and to store partially filtered pixels corresponding to a set of partially filtered macroblocks. An edge order controller in the de-blocking filter is configured to load the pixels corresponding to the set of sub-blocks into a filter engine from the internal pixel buffer, to filter the set of sub-blocks, such that, at least one horizontal edge is filtered before filtering all vertical edges of the set of sub-blocks.

公开(公告)号：US09973754B2

公开(公告)日：2018-05-15

申请号：US14661711

申请日：2015-03-18

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mihir Narendra Mody ,  Niraj Nandan ,  Mahesh Madhukar Mehendale ,  Subrangshu Das ,  Dipan Kumar Mandal ,  Pavan Venkata Shastry

IPC: H04N19/115 ,  H04N19/423 ,  G06F13/28

CPC classification number: H04N19/115 ,  G06F13/28 ,  H04N19/423

Abstract: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.

公开(公告)号：US09854252B2

公开(公告)日：2017-12-26

申请号：US14282211

申请日：2014-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/17 ,  H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/82 ,  H04N19/86 ,  H04N19/186

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/14 ,  H04N19/186 ,  H04N19/82 ,  H04N19/86

Abstract: A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

公开(公告)号：US20170132754A1

公开(公告)日：2017-05-11

申请号：US15143491

申请日：2016-04-29

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Brian Chae ,  Shashank Dabral ,  Niraj Nandan ,  Hetul Sanghvi

IPC: G06T3/40 ,  G06T1/60 ,  G06T1/20

Abstract: An apparatus for scaling images is provided that includes at least two input ports, a scaling component coupled to the at least two input ports, the scaling component including a plurality of scalers, the scaling component configurable to map any scaler to any input port of the at least two input ports and configurable to map more than one scaler to any input port, and a memory coupled to the at least two input ports and to outputs of the plurality of scalers, the memory configured to store image data for each input port and scaled image data output by the plurality of scalers.

公开(公告)号：US09473784B2

公开(公告)日：2016-10-18

申请号：US14279318

申请日：2014-05-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/89 ,  H04N19/14 ,  H04N19/82 ,  H04N19/436 ,  H04N19/176 ,  H04N19/117 ,  H04N19/186 ,  H04N19/182 ,  H04N19/423 ,  H04N19/102

CPC classification number: H04N19/436 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/423 ,  H04N19/82

Abstract: A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by the SAO component, an indication that deblocked pixel blocks of an LCU are available, and applying SAO filtering, by the SAO component, to each pixel block of pixel blocks of an SAO processing area corresponding to the LCU responsive to the indication, wherein pixels of each pixel block of the SAO processing area are filtered in parallel.

Abstract translation: 提供了一种用于在SAO组件中的视频帧的最大编码单元（LCU）的采样自适应偏移（SAO）滤波的方法，其包括由SAO组件接收到LCU的解块像素块可用的指示，以及应用 通过SAO分量对SAO处理区域的对应于该LCU的SAO处理区域的每个像素块进行SAO滤波，其中SAO处理区域的每个像素块的像素被并行地滤波。