SYSTEM AND METHOD FOR MANAGING CACHE
    1.
    发明申请
    SYSTEM AND METHOD FOR MANAGING CACHE 有权
    用于管理缓存的系统和方法

    公开(公告)号:US20150339234A1

    公开(公告)日:2015-11-26

    申请号:US14583020

    申请日:2014-12-24

    IPC分类号: G06F12/08

    摘要: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.

    摘要翻译: 系统包括第一和第二处理组件,基于限定的分离器组件,第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。

    System and method for managing cache
    3.
    发明授权
    System and method for managing cache 有权
    用于管理缓存的系统和方法

    公开(公告)号:US09430393B2

    公开(公告)日:2016-08-30

    申请号:US14583020

    申请日:2014-12-24

    IPC分类号: G06F12/08 G06F3/06

    摘要: A system includes first and second processing components, a qualified based splitter component, a first and second configurable cache element and an arbiter component. The first data processing component generates a first request for a first portion of data at a first location within a memory. The second data processing component generates a second request for a second portion of data at a second location within the memory. The qualifier based splitter component routes the first request and the second request based on a qualifier. The first configurable cache element enables or disables prefetching data within a first region of the memory. The second configurable cache element enables or disables prefetching data within a second region of the memory. The arbiter component routes the first request and the second request to the memory.

    摘要翻译: 系统包括第一和第二处理组件,基于限定的分离器组件,第一和第二可配置高速缓存元件和仲裁器组件。 第一数据处理组件在存储器内的第一位置处生成对数据的第一部分的第一请求。 第二数据处理组件在存储器内的第二位置产生第二数据部分的第二请求。 基于限定符的分离器组件基于限定符路由第一请求和第二请求。 第一可配置缓存元件启用或禁用在存储器的第一区域内的预取数据。 第二可配置高速缓存元件在存储器的第二区域内启用或禁用预取数据。 仲裁器组件将第一个请求和第二个请求路由到内存。

    DYNAMIC FRAME PADDING IN A VIDEO HARDWARE ENGINE
    8.
    发明申请
    DYNAMIC FRAME PADDING IN A VIDEO HARDWARE ENGINE 审中-公开
    视频硬件引擎中的动态框架

    公开(公告)号:US20150271512A1

    公开(公告)日:2015-09-24

    申请号:US14661770

    申请日:2015-03-18

    IPC分类号: H04N19/46 H04N19/51

    CPC分类号: H04N19/43 H04N19/51

    摘要: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

    摘要翻译: 公开了支持动态帧填充的视频硬件引擎。 视频硬件引擎包括外部存储器。 外部存储器存储参考帧。 参考帧包括多个参考像素。 运动估计(ME)引擎接收当前LCU(最大编码单元),并且定义当前LCU周围的运动估计周围的搜索区域。 ME引擎接收与当前LCU对应的一组参考像素。 从外部存储器接收多个参考像素的参考像素集合。 当搜索区域的一部分区域在参考帧之外时,ME引擎沿着参考帧的边缘焊接一组重复像素。

    LOW POWER ULTRA-HD VIDEO HARDWARE ENGINE
    9.
    发明申请
    LOW POWER ULTRA-HD VIDEO HARDWARE ENGINE 有权
    低功率超高清视频硬件引擎

    公开(公告)号:US20150271494A1

    公开(公告)日:2015-09-24

    申请号:US14661711

    申请日:2015-03-18

    摘要: A low power video hardware engine is disclosed. The video hardware engine includes a video hardware accelerator unit. A shared memory is coupled to the video hardware accelerator unit, and a scrambler is coupled to the shared memory. A vDMA (video direct memory access) engine is coupled to the scrambler, and an external memory is coupled to the vDMA engine. The scrambler receives an LCU (largest coding unit) from the vDMA engine. The LCU comprises N×N pixels, and the scrambler scrambles N×N pixels in the LCU to generate a plurality of blocks with M×M pixels. N and M are integers and M is less than N.

    摘要翻译: 公开了一种低功率视频硬件引擎。 视频硬件引擎包括视频硬件加速器单元。 共享存储器耦合到视频硬件加速器单元,并且加扰器耦合到共享存储器。 vDMA(视频直接存储器访问)引擎耦合到加扰器,并且外部存储器耦合到vDMA引擎。 加扰器从vDMA引擎接收LCU(最大编码单元)。 LCU包括N×N个像素,扰频器对LCU中的N×N个像素进行加扰,以产生具有M×M个像素的多个块。 N和M是整数,M小于N.