公开(公告)号：US4999519A

公开(公告)日：1991-03-12

申请号：US277992

申请日：1988-11-30

申请人： Goro Kitsukawa ,  Kazumasa Yanagisawa ,  Takayuki Kawahara ,  Ryoichi Hori ,  Yoshinobu Nakagome ,  Noriyuki Hamma ,  Kiyoo Itoh ,  Hiromi Tukada

发明人： Goro Kitsukawa ,  Kazumasa Yanagisawa ,  Takayuki Kawahara ,  Ryoichi Hori ,  Yoshinobu Nakagome ,  Noriyuki Hamma ,  Kiyoo Itoh ,  Hiromi Tukada

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： An ECL circuit wherein a current switch and an emitter follower are coupled, is so constructed that, in a standby mode, the current switch has its current cut off or rendered smaller than in an operating mode. In addition, the ECL circuit comprises means for decoupling a load resistance of the current switch and a base of the emitter follower in the case of cutting off the current of the current switch, or means for increasing the load resistance of the current switch in the case of rendering the current of the current switch smaller. The semiconductor circuit of the present invention can reduce the power consumption of the ECL circuit and can suppress fluctuations in the voltage levels of the outputs of the ECL circuit.

摘要翻译： 其中电流开关和射极跟随器耦合的ECL电路被构造成使得在待机模式中，电流开关的电流切断或变得比操作模式小。 此外，ECL电路包括在切断电流开关的电流的情况下解耦电流开关的负载电阻和射极跟随器的基极的装置，或用于增加电流开关的负载电阻的装置 使当前开关的电流变小的情况。 本发明的半导体电路可以降低ECL电路的功耗，并且可以抑制ECL电路的输出的电压电平的波动。

公开(公告)号：US4958325A

公开(公告)日：1990-09-18

申请号：US238375

申请日：1988-08-31

申请人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Masakazu Aoki ,  Shin'ichi Ikenaga ,  Masashi Horiguchi ,  Hitoshi Tanaka

发明人： Yoshinobu Nakagome ,  Kiyoo Itoh ,  Masakazu Aoki ,  Shin'ichi Ikenaga ,  Masashi Horiguchi ,  Hitoshi Tanaka

IPC分类号： G11C7/18 ,  G11C11/4097

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： A highly integrated semiconductor memory, particularly, a low noise dynamic memory. As the density of integration of the dynamic memory increases, the distance between data lines decreases and a new type of noise, which has hitherto been thought little of, displays itself. To cope with this problem in the semiconductor memory comprising a plurality of pairs of data lines arranged in substantially parallel relationship with each other, respective pairs having substantially the same electric characteristics, connection means provided in association with the respective data line pairs, a plurality of word lines laid to extend perpendicularly to the data line pairs, at least one memory cell connected to at least one of intersections of the word lines with data lines of the pairs, and a plurality of sense amplifier means respectively connected to the data line pairs to differentially detect signal voltages appearing on each data line pair, the plural data line pairs have an alternate arrangement of a pair of data lines transposed at an even number of places and a pair of data lines transposed at an odd number of places, and the sense amplifier means is operative to change voltage on one of the data lines of a pair to a high-level voltage and voltage on the other of the data lines of the pair of a low-level voltage.

摘要翻译： 高度集成的半导体存储器，特别是低噪声动态存储器。 随着动态存储器的集成密度增加，数据线之间的距离减小，而迄今为止被认为很少的新型噪声显示出来。 为了在包括彼此基本上平行关系的多对数据线的半导体存储器中应对这个问题，具有基本上相同电特性的各对具有与各个数据线对相关联地设置的连接装置， 与数据线对垂直延伸的字线，至少一个存储单元连接到字线与该对的数据线的交点中的至少一个，以及分别连接到数据线对的多个读出放大器装置 差分检测每个数据线对上出现的信号电压，多个数据线对具有在偶数个位置处置换的一对数据线和在奇数个位置处置换的一对数据线的交替排列，并且感测 放大器装置可操作以将一对数据线之一上的电压改变为ot上的高电平电压和电压 她的数据线是一对低电平的电压。

公开(公告)号：US4636985A

公开(公告)日：1987-01-13

申请号：US648361

申请日：1984-09-07

申请人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masahi Horiguchi ,  Toshifumi Ozaki ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

发明人： Masakazu Aoki ,  Yoshinobu Nakagome ,  Masahi Horiguchi ,  Toshifumi Ozaki ,  Katsuhiro Shimohigashi ,  Shinichi Ikenaga

IPC分类号： G11C7/06 ,  G11C7/22 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/06 ,  H01L27/108

摘要： In a semiconductor memory in which a large number of memory cells are arrayed in the shape of a matrix, arrangements are provided for a high-sensitivity read-out. In one embodiment, a writing circuit, a voltage amplifier and a sense amplifier are successively connected to a data line that connects input and output ends of the memory cells in an identical row, with the voltage amplifier being formed as a CTD voltage amplifier that is composed of two charge transfer gates and a driving gate located between them. In accordance with another embodiment, a charge supplying circuit and a charge transfer circuit can be coupled between the memory cells and the sense amplifier to allow information transfer without any substantial loss.

摘要翻译： 在其中以矩阵形式排列大量存储单元的半导体存储器中，提供了用于高灵敏度读出的布置。 在一个实施例中，写入电路，电压放大器和读出放大器连续地连接到连接存储器单元的输入和输出端相同行的数据线，电压放大器形成为CTD电压放大器 由两个电荷转移门和位于它们之间的驱动门组成。 根据另一个实施例，电荷供应电路和电荷转移电路可以耦合在存储器单元和读出放大器之间以允许信息传输而没有任何实质的损失。