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公开(公告)号：US07511689B2
公开(公告)日：2009-03-31
申请号：US11976113
申请日：2007-10-22
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G2300/0814 , G09G2300/0819 , G09G2320/0233
摘要： A display device includes a pixel array unit and a peripheral circuit unit. The pixel array unit includes first scanning lines arranged in rows; second scanning lines arranged in rows; signal lines arranged in columns; and pixels arranged in a matrix pattern at intersections of the scanning lines and the signal lines. The peripheral circuit unit includes a first scanner to supply first control pulses to the first scanning lines; a second scanner to supply second control pulses to the second scanning lines; and a signal driver to supply video signals to the signal lines. Each of the pixels includes at least a sampling transistor; a driving transistor; an emission time controlling transistor; a holding capacitance; and a light-emitting element.
摘要翻译： 显示装置包括像素阵列单元和外围电路单元。 像素阵列单元包括排列成行的第一扫描线; 排列成行的第二扫描线; 信号线排列成列; 以及在扫描线和信号线的交点处以矩阵图案排列的像素。 外围电路单元包括：第一扫描器，用于向第一扫描线提供第一控制脉冲; 第二扫描器，用于向第二扫描线提供第二控制脉冲; 以及向信号线提供视频信号的信号驱动器。 每个像素至少包括采样晶体管; 一个驱动晶体管; 发射时间控制晶体管; 保持电容; 和发光元件。
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公开(公告)号：US20080278410A1
公开(公告)日：2008-11-13
申请号：US12081927
申请日：2008-04-23
IPC分类号： G09G3/20
CPC分类号： H01L27/3276 , G09G3/3233 , G09G2300/043 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2320/043 , H01L27/124 , H01L51/0023 , H01L2227/323 , H01L2251/568
摘要： A display is disclosed, having an interconnect layout that allows easy repairing of a short-circuit defect even at the intersection of row and column interconnects. The display includes: row interconnects configured to be disposed along rows; column interconnects configured to be disposed along columns; and pixels configured to be disposed corresponding to intersections of the row and column interconnects arranged in a lattice manner. Each of the pixels includes at least a sampling transistor, a drive transistor, a holding capacitor, and a light-emitting element. The sampling transistor is turned on in response to a control signal supplied from one of the interconnects to thereby sample a video signal supplied from another of the interconnects and write the video signal to the holding capacitor. The drive transistor supplies the light-emitting element with a drive current dependent upon the video signal written to the holding capacitor.
摘要翻译： 公开了一种具有互连布局的显示器，即使在行和列互连的交叉处，也能够容易地修复短路缺陷。 显示器包括：配置成沿着行布置的行互连; 列互连配置成沿着列设置; 以及被配置为对应于以格子状布置的行和列互连的交叉点设置的像素。 每个像素至少包括采样晶体管，驱动晶体管，保持电容器和发光元件。 采样晶体管响应于从互连之一提供的控制信号而导通，从而对从另一个互连提供的视频信号进行采样，并将视频信号写入保持电容器。 驱动晶体管根据写入保持电容器的视频信号向发光元件提供驱动电流。
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公开(公告)号：US07420534B2
公开(公告)日：2008-09-02
申请号：US10441420
申请日：2003-05-20
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3648 , G09G2310/06
摘要： A vertical driving circuit 5 includes: a shift register 5R having a multistage-connected structure with one stage corresponding to two gate lines G, for transferring a start pulse 2VST inputted to a first stage SR1 thereof and sequentially outputting shift pulses R1 and R2 from respective stages; an intermediate gate circuit unit 5T disposed so as to correspond to each stage of the shift register, for processing a shift pulse of one stage and a shift pulse of a preceding stage and thereby generating temporally separate intermediate pulses A and B in respective stages; and an output gate circuit unit 5U for processing the intermediate pulses A and B and thereby sequentially outputting drive pulses P1 to P4 to four corresponding gate lines G to sequentially select pixels. The shift register 5R includes a dummy additional stage SR0 disposed in front of the first stage SR1 thereof, and a shift pulse R0 outputted from the additional stage is supplied to a first stage NAND1 of the intermediate gate circuit unit, whereby a normal intermediate pulse A is outputted from the first stage of the intermediate gate circuit unit.
摘要翻译： 垂直驱动电路5包括：具有多级连接结构的移位寄存器5R，其一级对应于两条栅极线G，用于传送输入到其第一级SR 1的起始脉冲2 VST，并顺序地输出移位脉冲R 1 和R 2; 设置成对应于移位寄存器的各级的中间门电路单元5T，用于处理一级的移位脉冲和前级的移位脉冲，从而在各个阶段中产生时间上分离的中间脉冲A和B. 以及用于处理中间脉冲A和B的输出门电路单元5U，从而顺序地将驱动脉冲P 1至P 4输出到四个对应的栅极线G以顺序地选择像素。 移位寄存器5R包括设置在其第一级SR 1之前的虚设附加级SR 0，并且从附加级输出的移位脉冲R 0被提供给中间门电路单元的第一级NAND 1，由此 从中间门电路单元的第一级输出正常的中间脉冲A.
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114.发明申请公开(公告)号：US20080198104A1
公开(公告)日：2008-08-21
申请号：US12071284
申请日：2008-02-19
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G3/3208 , G09G3/3258 , G09G5/10 , G09G2300/0819 , G09G2300/0861 , G09G2310/0289 , G09G2320/0214 , G09G2320/0233 , H01L27/1255 , H01L27/322 , H01L27/3248 , H01L27/3258 , H01L27/3262 , H01L27/3265 , H01L27/3276 , H01L51/5228 , H01L51/524 , H01L51/5246
摘要： In a display apparatus including a correction unit and a switching transistor, the correction unit operates in a non-light emission period such that a correction voltage for eliminating an effect of a variation in a characteristic of a driving transistor is stored in a storage capacitor. The switching transistor is disposed between one current terminal of the driving transistor and a light emitting element. The switching transistor turns off during the non-light emission period thereby to electrically disconnect the light emitting element from the one current terminal of the driving transistor thereby preventing a leakage current from flowing through the light emitting element during the period in which the correction unit operates, and thus preventing the correction voltage from having an error due to the leakage current.
摘要翻译： 在包括校正单元和开关晶体管的显示装置中，校正单元在非发光时段中工作，使得用于消除驱动晶体管的特性变化的影响的校正电压被存储在存储电容器中。 开关晶体管设置在驱动晶体管的一个电流端子和发光元件之间。 开关晶体管在非发光时段期间截止，从而使发光元件与驱动晶体管的一个电流端电气断开，从而防止在校正单元操作期间漏电流流过发光元件 ，从而防止校正电压由于漏电流而产生误差。
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公开(公告)号：US07414605B2
公开(公告)日：2008-08-19
申请号：US10755439
申请日：2004-01-13
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3648 , G09G2300/0842 , G09G2310/0275 , G09G2310/06 , G09G2320/02 , G09G2320/0223
摘要： To prevent a vertical stripe pattern on a display screen of an image display device and an image display panel of narrow pulse driving, there is provided an image display panel and image display device comprising a pixel portion arranged with pixels in matrix, a drive circuit connected respectively to each data line shared by pixels in each column of the pixel portion for controlling supplying of a video signal to be input to the data line based on a plurality of clocks to be input, a plurality of input pads for inputting a plurality of clocks, and a clock input circuit, wherein resistance of wiring from the plurality of input pads to the clock input circuits is made to be approximately the same between the plurality of clocks.
摘要翻译： 为了防止图像显示装置的显示屏幕和窄脉冲驱动的图像显示面板上的垂直条纹图案，提供了一种图像显示面板和图像显示装置，其包括以矩阵形式排列的像素部分，驱动电路连接 分别对应于每个像素部分的各列中的像素共享的每个数据线，用于基于要输入的多个时钟控制提供要输入到数据线的视频信号;多个输入焊盘，用于输入多个时钟 以及时钟输入电路，其中使得从多个输入焊盘到时钟输入电路的布线的电阻在多个时钟之间大致相同。
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公开(公告)号：US07382342B2
公开(公告)日：2008-06-03
申请号：US10857857
申请日：2004-06-02
IPC分类号： G09G3/36 , G02F1/1345
CPC分类号： G09G3/3233 , G09G3/30 , G09G3/3208 , G09G3/3266 , G09G2300/0417 , G09G2300/0426 , G09G2300/043 , G09G2300/0439 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0256 , G09G2320/043 , G09G2330/028
摘要： A pixel circuit able to prevent a spread of the terminal voltages of drive transistors inside a panel and in turn able to reliably prevent deterioration of uniformity, wherein a source of a TFT serving as a drive transistor is connected to an anode of a light emitting element, a drain is connected to a power source potential, a capacitor is connected between a gate and source of the TFT, and a source potential of the TFT is connected to a fixed potential through a TFT serving as a switch transistor and wherein pixel circuit lines are connected by an upper line and bottom line and are arranged in parallel with pixel circuit power source voltage lines so as not to have intersecting parts.
摘要翻译： 一种像素电路，其能够防止驱动晶体管在面板内部的端子电压的扩展，从而能够可靠地防止均匀性的劣化，其中用作驱动晶体管的TFT的源极连接到发光元件的阳极 漏极连接到电源电位，电容器连接在TFT的栅极和源极之间，TFT的源极电位通过用作开关晶体管的TFT连接到固定电位，并且其中像素电路线 通过上线和底线连接并且与像素电路电源电压线并联布置，以便不具有相交部分。
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公开(公告)号：US20080042948A1
公开(公告)日：2008-02-21
申请号：US11890491
申请日：2007-08-07
IPC分类号： G09G3/32
CPC分类号： G09G3/3233 , G09G3/3266 , G09G2300/0426 , G09G2300/0439 , G09G2300/0819 , G09G2300/0861 , G09G2300/0866 , G09G2310/0262 , G09G2310/0289 , G09G2320/0223 , G09G2320/043
摘要： A display device is disclosed. The display device includes: a pixel array part; and a drive part that drives the pixel array part. The pixel array part includes row-wise first scan lines and second scan lines, column-wise signal lines, pixels arranged in a matrix form on parts where the lines intersect, and power supply lines and ground lines that supply power to the respective pixels. The drive part includes a first scanner that sequentially supplies first control signals to the respective first scan lines and line-sequentially scans the pixels in units of rows, a second scanner that sequentially supplies second control signals to the respective second scan lines according to the line-sequential scan, and a signal selector that supplies video signals to the column-wise signal lines according to the line-sequential scan.
摘要翻译： 公开了一种显示装置。 显示装置包括：像素阵列部分; 以及驱动像素阵列部的驱动部。 像素阵列部分包括行方向的第一扫描线和第二扫描线，列方向信号线，以矩阵形式布置在线交叉的部分上的像素，以及向各个像素供电的电源线和接地线。 驱动部分包括第一扫描器，其顺序地将第一控制信号提供给相应的第一扫描线并且以行为单位对像素进行行顺序扫描;第二扫描器，根据该行顺序地将第二控制信号提供给相应的第二扫描线 以及根据线顺序扫描向视频信号线提供视频信号的信号选择器。
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公开(公告)号：US20080001861A1
公开(公告)日：2008-01-03
申请号：US11798822
申请日：2007-05-17
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G3/2014 , G09G3/3266 , G09G2300/0819 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2320/0233
摘要： Herein disclosed an image display apparatus, including a pixel array section, and a peripheral circuit section. The pixel array section has a plurality of scanning lines extending along rows, a plurality of signal lines extending along columns, and a plurality of pixels disposed in a matrix at locations at which the scanning lines and the signal lines intersect with each other. The peripheral circuit section has a scanner and a driver. Each of the pixels contains a sampling transistor, a drive transistor, a switching transistor, and a light emitting element.
摘要翻译： 这里公开了包括像素阵列部分和外围电路部分的图像显示装置。 像素阵列部分具有沿行延伸的多条扫描线，沿着列延伸的多条信号线，以及在扫描线和信号线彼此相交的位置处以矩阵形式布置的多个像素。 外围电路部分具有扫描器和驱动器。 每个像素包含采样晶体管，驱动晶体管，开关晶体管和发光元件。
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119.发明授权Display apparatus including plural pixel simultaneous sampling method and wiring method 失效显示装置，包括多个像素同时采样方法和布线方法公开(公告)号：US07218309B2
公开(公告)日：2007-05-15
申请号：US10271198
申请日：2002-10-15
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G2310/0248 , G09G2310/0275 , G09G2320/0223 , G09G2320/0257 , G09G2352/00
摘要： A display apparatus employing a plural pixel simultaneous sampling method is disclosed wherein the parasitic capacitance of each wiring line is reduced to suppress a ghost. A sampling switch set includes switches which are connected to corresponding ones of signal lines and video lines. Upper and lower side horizontal drive circuits drive switches of the sampling switch set simultaneously to sample the video signals of systems to the corresponding signal lines, and perform sampling successively for each signal lines to write the video signals into pixels of the selected row. The video lines are divided into two groups of video lines disposed on the upper and lower sides. The upper side video lines are connected to corresponding even-numbered ones of the signal lines through the corresponding switches while the lower side video lines are connected to corresponding odd-numbered ones of the signal lines through the corresponding switches.
摘要翻译： 公开了一种采用多像素同时采样方法的显示装置，其中每个布线的寄生电容被减小以抑制重影。 采样开关组包括连接到相应信号线和视频线的开关。 上下水平驱动电路同时驱动采样开关组的开关，将系统的视频信号采样到相应的信号线，并对每个信号线连续进行采样，将视频信号写入所选行的像素。 视频线被分成设置在上侧和下侧的两组视频线。 上侧视频线通过相应的开关连接到相应的偶数信号线，而下侧视频线通过相应的开关连接到相应的奇数信号线。
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120.发明申请Pixel circuit, display device, driving method of pixel circuit, and driving method of display device 有权像素电路，显示装置，像素电路的驱动方法以及显示装置的驱动方法公开(公告)号：US20060022907A1
公开(公告)日：2006-02-02
申请号：US11171416
申请日：2005-07-01
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G3/3258 , G09G3/3266 , G09G3/3291 , G09G2300/0417 , G09G2300/0426 , G09G2300/0819 , G09G2300/0852 , G09G2310/02 , G09G2310/06 , G09G2320/043 , G09G2330/028
摘要： A pixel circuit disposed at a part where a scanning line and a signal line intersect each other includes at least an electrooptic element, a drive transistor, a sampling transistor, and a retaining capacitance. The drive transistor has a gate connected to an input node, a source connected to an output node, and a drain connected to a predetermined power supply potential and supplies a driving current to the electrooptic element according to a signal potential retained in the retaining capacitance. The electrooptic element has one terminal connected to the output node and another terminal connected to a predetermined potential. The sampling transistor is connected between the input node and the signal line and operates when selected by the scanning line, samples an input signal from the signal line, and retains the input signal in the retaining capacitance. The retaining capacitance is connected to the input node. The pixel circuit further includes a compensating circuit which detects a decrease in the driving current from a side of the output node, and feeds back a result of detection to a side of the input node, for compensating for a decrease in the driving current which decrease is attendant on a secular change of the drive transistor.
摘要翻译： 布置在扫描线和信号线彼此相交的部分的像素电路至少包括电光元件，驱动晶体管，采样晶体管和保持电容。 驱动晶体管具有连接到输入节点的栅极，连接到输出节点的源极和连接到预定电源电位的漏极，并且根据保持电容中保持的信号电位向电光元件提供驱动电流。 电光元件具有连接到输出节点的一个端子和连接到预定电位的另一端子。 采样晶体管连接在输入节点和信号线之间，并在扫描线选择时进行工作，对来自信号线的输入信号进行采样，并将输入信号保持在保持电容中。 保持电容连接到输入节点。 像素电路还包括补偿电路，其检测来自输出节点侧的驱动电流的减小，并将检测结果反馈到输入节点的一侧，以补偿减小的驱动电流 伴随着驱动晶体管的长期变化。
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