Transistor amplifier
    121.
    发明授权

    公开(公告)号:US10911005B2

    公开(公告)日:2021-02-02

    申请号:US16427596

    申请日:2019-05-31

    Abstract: A transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The transistor amplifier exhibits improved input impedance and improved linearity.

    Sound reputation
    123.
    发明授权

    公开(公告)号:US10887334B2

    公开(公告)日:2021-01-05

    申请号:US16123099

    申请日:2018-09-06

    Abstract: A cybersecurity system and method utilizing SOUND reputation, where a set of reputations are associated with each actor on a network. The actors on a network may be users, hosts, applications, and the like. The associated reputations are aggregated and updated as new information about an actor's activity is reported according to a defined and modifiable protocol, or policy. The actor's activity may be reported by one or more threat sensors. The effect of a particular misbehavior can be tuned to match the needs of the specific network. When a bad actor's reputation sinks too low, the system can take whatever action is appropriate: reports can be sent, an operator can be notified, the offender can be cut off from the network, or the like.

    Multi-hop security amplification
    124.
    发明授权

    公开(公告)号:US10887091B2

    公开(公告)日:2021-01-05

    申请号:US16200984

    申请日:2018-11-27

    Abstract: Techniques are disclosed for multi-hop security amplification. The techniques disclosed provide multi-hop security amplification by applying a secret sharing scheme to data as the data is routed within a network to an intended recipient device. In an embodiment, a sending device divides the data into shares based on a secret sharing scheme, and sends the shares to respective network nodes in a network. These network nodes then divide their respective shares into lower-level shares based on the secret sharing scheme, and route the lower-level shares to downstream network nodes for further routing to the intended recipient device. The intended recipient device receives some or all of the lower-level shares and reconstructs the data from the received lower-level shares. In an embodiment, the secret sharing scheme is a threshold-based secret sharing scheme, such as Shamir's secret sharing scheme.

    Geolocation using time difference of arrival and long baseline interferometry

    公开(公告)号:US10884095B2

    公开(公告)日:2021-01-05

    申请号:US16352404

    申请日:2019-03-13

    Abstract: Techniques are provided for geolocation of a radar emitting source. A methodology implementing the techniques according to an embodiment includes calculating time difference of arrival (TDOAs) of ground emitter radar pulses, within a dwell period, between two long baseline interferometer (LBI) antennas. The TDOA calculations are based on a precision estimate of the time of arrival of the radar pulses. The method further includes calculating an LBI phase wrap disambiguation factor based on (1) the TDOAs, (2) an average of frequencies of the radar pulses within the dwell period, and (3) an average of phase shifts of the radar pulses between the LBI antennas within the dwell period. The method further includes mapping a curve of points onto the surface of the earth based on an LBI cone angle calculation employing the LBI phase wrap disambiguation factor. The curve of points is associated with a geolocation of the ground emitter.

    APPARATUS AND METHOD FOR REDUCING RADIATION INDUCED MULTIPLE-BIT MEMORY SOFT ERRORS

    公开(公告)号:US20200379842A1

    公开(公告)日:2020-12-03

    申请号:US16425377

    申请日:2019-05-29

    Inventor: Jason F. Ross

    Abstract: A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros, without requiring novel, specialized memory designs and without significant added cost or performance loss. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core IC of an MCM-HIC, and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

    Fuze setter interface for powering and programming a fuze on a guided projectile

    公开(公告)号:US10852116B2

    公开(公告)日:2020-12-01

    申请号:US16294505

    申请日:2019-03-06

    Inventor: Francis M. Feda

    Abstract: A fuze setter interface for substantially simultaneously and wirelessly transferring power and data between a fuze setter and fuze. The fuze setter interface includes separate power and communications interfaces. In the power interface, an induction coil is provided in each of the fuze setter and fuze. Power is transferred by magnetic field coupling between the induction coils. In the communications interface, a communications member is provided in each of the fuze setter and fuze, along with appropriate functions to generate alternating-current (AC) waveforms, and condition, modulate or demodulate signals. In one example, both communications members are induction coils that transfer data by magnetic field coupling. In another example, both communications members are radio-frequency (RF) transceivers that transfer data by radio signal. The RF transceiver in the fuze may be a Height of Burst (HoB) sensor. In another example, both communications members are optical transceivers that transfer data by optical signal.

    DEBUG INTERFACE RECORDER AND REPLAY UNIT
    130.
    发明申请

    公开(公告)号:US20200371159A1

    公开(公告)日:2020-11-26

    申请号:US16420362

    申请日:2019-05-23

    Abstract: The system and method of using a debug interface recorder and replay unit for debugging and testing devices of interest such as integrated circuits by using a debug interface buffer controller to receive, record, and replay sequences of instructions to the integrated circuit. This is particularly useful for deployed devices that are difficult or dangerous to access. This is also beneficial for devices that cannot be reached (e.g., after launch). By recording sequences and storing them for later use, and by communicating commands and configuration settings to a device, system maintenance and troubleshooting is accomplished saving valuable time and money without requiring physical access to the device of interest.

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